Re: [PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V

On 28 June 2018 at 09:31, Stefan Agner wrote: > The uSDHC supports DDR modes for eMMC devices running at 3.3V. This > allows to run eMMC with 3.3V signaling voltage at DDR52 mode: > > # cat /sys/kernel/debug/mmc1/ios > clock: 5200 Hz > vdd:21 (3.3 ~ 3.4 V) > bus mo

[PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V

The uSDHC supports DDR modes for eMMC devices running at 3.3V. This allows to run eMMC with 3.3V signaling voltage at DDR52 mode: # cat /sys/kernel/debug/mmc1/ios clock: 5200 Hz vdd:21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select:0 (don't care) p