On 20 November 2018 at 15:55, Sjoerd Simons
wrote:
> On Tue, 2018-11-20 at 15:24 +0100, Ulf Hansson wrote:
>> On 20 November 2018 at 15:00, Sjoerd Simons
>> wrote:
>> > On Tue, 2018-11-20 at 14:08 +0100, Ulf Hansson wrote:
>> > > + Hal Emmerich
>> > >
>> > > On 20 November 2018 at 12:38, Sjoerd S
On Tue, 2018-11-20 at 15:24 +0100, Ulf Hansson wrote:
> On 20 November 2018 at 15:00, Sjoerd Simons
> wrote:
> > On Tue, 2018-11-20 at 14:08 +0100, Ulf Hansson wrote:
> > > + Hal Emmerich
> > >
> > > On 20 November 2018 at 12:38, Sjoerd Simons
> > > wrote:
> > > > On Tue, 2018-11-20 at 11:23 +01
On 20 November 2018 at 15:00, Sjoerd Simons
wrote:
> On Tue, 2018-11-20 at 14:08 +0100, Ulf Hansson wrote:
>> + Hal Emmerich
>>
>> On 20 November 2018 at 12:38, Sjoerd Simons
>> wrote:
>> > On Tue, 2018-11-20 at 11:23 +0100, Wolfram Sang wrote:
>> > > > > >
>> > So if you know the pattern, or jus
On Tue, 2018-11-20 at 14:08 +0100, Ulf Hansson wrote:
> + Hal Emmerich
>
> On 20 November 2018 at 12:38, Sjoerd Simons
> wrote:
> > On Tue, 2018-11-20 at 11:23 +0100, Wolfram Sang wrote:
> > > > > >
> > So if you know the pattern, or just happen to hit it often in e.g.
> > automated testing, it
+ Hal Emmerich
On 20 November 2018 at 12:38, Sjoerd Simons
wrote:
> On Tue, 2018-11-20 at 11:23 +0100, Wolfram Sang wrote:
>> > > > That also happens to be one of the cards we deploy; However i
>> > > > did
>> > > > wonder about adding a quirk but decided against it as it was
>> > > > not clear
>
On Tue, 2018-11-20 at 11:23 +0100, Wolfram Sang wrote:
> > > > That also happens to be one of the cards we deploy; However i
> > > > did
> > > > wonder about adding a quirk but decided against it as it was
> > > > not clear
> > > > to me from the specification that CACHE ON really is meant to
> > >
> > No strong opinion. Especially not if you say it is in the spec (although
> > "must be sufficient" would be better than "should be" ;)). Also, I
> > assume this failure is reproducible and should turn up during
> > development? Compared to "happens once in a while randomly"?
>
> At least for m
Hi,
On 20/11/18 3:53 PM, Wolfram Sang wrote:
>
That also happens to be one of the cards we deploy; However i did
wonder about adding a quirk but decided against it as it was not clear
to me from the specification that CACHE ON really is meant to complete
within GENERIC_CMD6_TI
> >> That also happens to be one of the cards we deploy; However i did
> >> wonder about adding a quirk but decided against it as it was not clear
> >> to me from the specification that CACHE ON really is meant to complete
> >> within GENERIC_CMD6_TIMEOUT. That and i fret about ending up in hit-a-
Hi Uffe,
On 20/11/18 2:54 PM, Ulf Hansson wrote:
> On 7 November 2018 at 09:47, Wolfram Sang wrote:
>>
>>> That also happens to be one of the cards we deploy; However i did
>>> wonder about adding a quirk but decided against it as it was not clear
>>> to me from the specification that CACHE ON re
On 7 November 2018 at 09:47, Wolfram Sang wrote:
>
>> That also happens to be one of the cards we deploy; However i did
>> wonder about adding a quirk but decided against it as it was not clear
>> to me from the specification that CACHE ON really is meant to complete
>> within GENERIC_CMD6_TIMEOUT
> That also happens to be one of the cards we deploy; However i did
> wonder about adding a quirk but decided against it as it was not clear
> to me from the specification that CACHE ON really is meant to complete
> within GENERIC_CMD6_TIMEOUT. That and i fret about ending up in hit-a-
> mole game
On Tue, 2018-11-06 at 19:34 +0530, Faiz Abbas wrote:
> Hi Sjoerd,
>
> On Tuesday 06 November 2018 07:00 PM, Sjoerd Simons wrote:
> > On some of our boards containing Micron eMMC chips compatible with
> > the eMMC 5.0 specification we starting seeing boot failures due to
> > timeouts:
> > mmc1: e
Hi Sjoerd,
On Tuesday 06 November 2018 07:00 PM, Sjoerd Simons wrote:
> On some of our boards containing Micron eMMC chips compatible with
> the eMMC 5.0 specification we starting seeing boot failures due to
> timeouts:
> mmc1: error -110 whilst initialising MMC card
>
> It turns out that switc
On some of our boards containing Micron eMMC chips compatible with
the eMMC 5.0 specification we starting seeing boot failures due to
timeouts:
mmc1: error -110 whilst initialising MMC card
It turns out that switching the cache on after a power loss event can
take quite long. In some simple test
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