On Mon, Oct 12, 2020 at 1:14 PM Alexander Monakov wrote:
>
> On Mon, 12 Oct 2020, Rafael J. Wysocki wrote:
>
> > > @@ -20,7 +20,11 @@
> > > * All CPUs have same idle states as boot CPU
> > > *
> > > * Chipset BM_STS (bus master status) bit is a NOP
> > > - * for preventing entry into dee
On Mon, 12 Oct 2020, Rafael J. Wysocki wrote:
> > @@ -20,7 +20,11 @@
> > * All CPUs have same idle states as boot CPU
> > *
> > * Chipset BM_STS (bus master status) bit is a NOP
> > - * for preventing entry into deep C-stats
> > + * for preventing entry into deep C-states
> > + *
> >
On Sun, Oct 11, 2020 at 1:13 AM Alexander Monakov wrote:
>
> Intel SDM does not explicitly say that entering a C-state via MWAIT will
> implicitly flush CPU caches as appropriate for that C-state. However,
> documentation for individual Intel CPU generations does mention this
> behavior.
>
> Since
Intel SDM does not explicitly say that entering a C-state via MWAIT will
implicitly flush CPU caches as appropriate for that C-state. However,
documentation for individual Intel CPU generations does mention this
behavior.
Since intel_idle binds to any Intel CPU with MWAIT, mention this
assumption
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