Hi Wolfram,
2016-09-23 21:12 GMT+09:00 Wolfram Sang :
> On Fri, Sep 23, 2016 at 09:04:01PM +0900, Masahiro Yamada wrote:
>> Currently, the status register FI2C_SR is checked immediately after
>> a STOP condition is issued in case of the deferred STOP condition.
>> It takes typically 5-10 usec unt
On Fri, Sep 23, 2016 at 09:04:01PM +0900, Masahiro Yamada wrote:
> Currently, the status register FI2C_SR is checked immediately after
> a STOP condition is issued in case of the deferred STOP condition.
> It takes typically 5-10 usec until the corresponding bits in the
> register are set, so the e
Currently, the status register FI2C_SR is checked immediately after
a STOP condition is issued in case of the deferred STOP condition.
It takes typically 5-10 usec until the corresponding bits in the
register are set, so the error check for "stop condition was not
completed" is very likely to be fa
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