On 10/14/2012 07:19 PM, Dmitry Fleytman wrote:
> There is a race condition in e1000 driver.
> It enables HW receive before RX rings initalization.
> In case of specific timing this may lead to host memory corruption
> due to DMA write to arbitrary memory location.
> Following patch fixes this issue
The datasheets for most of the parts are available at:
http://developer.intel.com/products/ethernet/resource.htm
You just need to select one of the parts supported by e1000 and select
either the datasheet or software developers manual depending on the part.
Thanks,
Alex
On 10/15/2012 01:20 PM,
Hello, Alex
Many thanks for clarification. I think your assumption is
correct and this is exactly what needs to be fixed in QEMU.
Is there any publicly available specification for Intel devices that
explains their operation in such a great details?
Dmitry.
On Mon, Oct 15, 2012 at 10:03 PM, Ale
Hello Dmitry,
My concern is that on many of our parts the behavior is to initialize
both the head and tail to 0, enable Rx for either the ring or device
depending on the queue configuration, and then allocate buffers and bump
tail to indicate that the new buffers are present. The reason behind
en
Hello, Alex
Originally this bug was reported for virtual machines running on top
of QEMU/KVM.
After patch preparation I've tested it on physical e1000 card and it
worked fine.
However, it could be I've missed something, as I see now other Intel
drivers (e1000e, ixgb, etc.)
use the same sequence (
On 10/14/2012 10:19 AM, Dmitry Fleytman wrote:
> There is a race condition in e1000 driver.
> It enables HW receive before RX rings initalization.
> In case of specific timing this may lead to host memory corruption
> due to DMA write to arbitrary memory location.
> Following patch fixes this issue
There is a race condition in e1000 driver.
It enables HW receive before RX rings initalization.
In case of specific timing this may lead to host memory corruption
due to DMA write to arbitrary memory location.
Following patch fixes this issue by reordering initialization steps.
Other Intel network
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