Re: [PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

2017-06-07 Thread Stephen Boyd
On 06/07, Dinh Nguyen wrote: > The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are > offset by 1 additional bit. > > Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and > Stratix10 platforms. > > Signed-off-by: Dinh Nguyen Some sort of Fixes: tag as w

[PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

2017-06-07 Thread Dinh Nguyen
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga/clk.