Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng: > The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. > > Reported-by: Lin Huang > Signed-off-by: Xing Zheng applied for 4.11 with Lin's test tag Thanks Heiko

[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c inde

Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

Tested-by: Lin Huang On 2017年01月18日 12:20, Xing Zheng wrote: The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/