Hi,
On Tue, Sep 15, 2020 at 7:10 AM elaine.zhang wrote:
>
> hi,
>
> We have two submissions which I hope will be helpful to you.
>
> https://patchwork.kernel.org/patch/11272465/
> https://patchwork.kernel.org/patch/11272471/
I can see this, I have reconstructed the fractional divider handling
fo
hi,
We have two submissions which I hope will be helpful to you.
https://patchwork.kernel.org/patch/11272465/
https://patchwork.kernel.org/patch/11272471/
A few more notes:
1. DCLK does not recommend the use of fractional frequency divider.
Generally, DCLK will monopolize a PLL, and the relat
在 2020/9/1 上午12:14, Jagan Teki 写道:
The current rockchip fractional approximation overflow the desired
rate if parent rate is lower than the (rate * 20) for few clocks like
dclk_vopb_frac.
The overflow condition has observed in px30 for dclk_vopb_frac
clock with an input rate of 71.1MHz and par
Quoting Jagan Teki (2020-08-31 09:14:36)
> The current rockchip fractional approximation overflow the desired
> rate if parent rate is lower than the (rate * 20) for few clocks like
> dclk_vopb_frac.
>
> The overflow condition has observed in px30 for dclk_vopb_frac
> clock with an input rate of 7
The current rockchip fractional approximation overflow the desired
rate if parent rate is lower than the (rate * 20) for few clocks like
dclk_vopb_frac.
The overflow condition has observed in px30 for dclk_vopb_frac
clock with an input rate of 71.1MHz and parent rate of 24MHz is,
[2.543280] r
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