Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Yixun Lan
Hi Martin On 11/07/17 06:03, Martin Blumenstingl wrote: > Hi Yixun, > > On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote: >> Hi Neil: >> >> >> On 11/06/17 16:57, Neil Armstrong wrote: >>> On 06/11/2017 08:52, Yixun Lan wrote: According to the datasheet, in Meson-GXBB/GXL series, The cl

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Martin Blumenstingl
Hi Yixun, On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote: > Hi Neil: > > > On 11/06/17 16:57, Neil Armstrong wrote: >> On 06/11/2017 08:52, Yixun Lan wrote: >>> According to the datasheet, in Meson-GXBB/GXL series, >>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >>> while clock gat

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Jerome Brunet
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote: > > * Is it an error in the published datasheets ? > > then, I think the published datasheet need to be updated. This needs to be clearly explained in your patch description/comment, or maybe directly in the code.

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Yixun Lan
Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >> >> Test passe

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Jerome Brunet
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote: > > > > > > Tested-by: Xingyu Chen > > > Signed-off-by: Yixun Lan > > > > Subject is missing "v2" tag and a reference to the previous message: > > 20171103181703.30434-1-yixun@amlogic.com > > > > Ok.. > I was considering this patch as a

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Yixun Lan
Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >> >> Test passe

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Yixun Lan
Hi Neil: On 11/06/17 16:57, Neil Armstrong wrote: > On 06/11/2017 08:52, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >> >> Test passed at gxl_skt d

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Jerome Brunet
On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: > According to the datasheet, in Meson-GXBB/GXL series, > The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], > while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. > > Test passed at gxl_skt dev board. I think this refer to a board nami

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-06 Thread Neil Armstrong
On 06/11/2017 08:52, Yixun Lan wrote: > According to the datasheet, in Meson-GXBB/GXL series, > The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], > while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. > > Test passed at gxl_skt dev board. > > Tested-by: Xingyu Chen > Signed-off-by: Yi

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-05 Thread Yixun Lan
According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl_skt dev board. Tested-by: Xingyu Chen Signed-off-by: Yixun Lan --- I think this error was introduced by a c

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

2017-11-05 Thread Yixun Lan
Hi Neil On 11/05/17 00:40, Neil Armstrong wrote: > Hi Yixun, > > Le 04/11/2017 09:41, Yixun Lan a écrit : >> >> >> On 11/04/17 02:17, Yixun Lan wrote: >>> According to the datasheet, the clock gate bit for >>> SARADC is bit[22] in Meson-GXBB/GXL series. >>> >>> Change-Id: Ic4fa58276d2a9ea273eef0a

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

2017-11-04 Thread Neil Armstrong
Hi Yixun, Le 04/11/2017 09:41, Yixun Lan a écrit : > > > On 11/04/17 02:17, Yixun Lan wrote: >> According to the datasheet, the clock gate bit for >> SARADC is bit[22] in Meson-GXBB/GXL series. >> >> Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 >> Signed-off-by: Yixun Lan >> --- >> dri

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

2017-11-04 Thread Yixun Lan
On 11/04/17 02:17, Yixun Lan wrote: > According to the datasheet, the clock gate bit for > SARADC is bit[22] in Meson-GXBB/GXL series. > > Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 > Signed-off-by: Yixun Lan > --- > drivers/clk/meson/gxbb.c | 2 +- > 1 file changed, 1 insertion(+),

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC

2017-11-03 Thread Yixun Lan
According to the datasheet, the clock gate bit for SARADC is bit[22] in Meson-GXBB/GXL series. Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.c b