Re: [PATCH] clk: at91: pll: fix input range validity check

2015-06-18 Thread Boris Brezillon
On Sun, 29 Mar 2015 03:53:43 +0200 Boris Brezillon wrote: > The PLL impose a certain input range to work correctly, but it appears that > this input range does not apply on the input clock (or parent clock) but > on the input clock after it has passed the PLL divisor. > Fix the implementation acc

Re: [PATCH] clk: at91: pll: fix input range validity check

2015-04-14 Thread Boris Brezillon
Hi Mike, On Sun, 12 Apr 2015 21:37:25 -0700 Michael Turquette wrote: > Quoting Boris Brezillon (2015-03-28 18:53:43) > > The PLL impose a certain input range to work correctly, but it appears that > > this input range does not apply on the input clock (or parent clock) but > > on the input clock

Re: [PATCH] clk: at91: pll: fix input range validity check

2015-04-12 Thread Michael Turquette
Quoting Boris Brezillon (2015-03-28 18:53:43) > The PLL impose a certain input range to work correctly, but it appears that > this input range does not apply on the input clock (or parent clock) but > on the input clock after it has passed the PLL divisor. > Fix the implementation accordingly. > >

[PATCH] clk: at91: pll: fix input range validity check

2015-03-28 Thread Boris Brezillon
The PLL impose a certain input range to work correctly, but it appears that this input range does not apply on the input clock (or parent clock) but on the input clock after it has passed the PLL divisor. Fix the implementation accordingly. Cc: # v3.14+ Signed-off-by: Boris Brezillon Reported-by