Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-17 Thread Stephen Boyd
Quoting eugen.hris...@microchip.com (2019-09-10 23:39:20) > From: Eugen Hristev > > The PLL input range needs to be able to allow 24 Mhz crystal as input > Update the range accordingly in plla characteristics struct > > Signed-off-by: Eugen Hristev > --- Applied to clk-next

Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-16 Thread Eugen.Hristev
On 16.09.2019 22:52, Stephen Boyd wrote: > Quoting eugen.hris...@microchip.com (2019-09-10 23:39:20) >> From: Eugen Hristev >> >> The PLL input range needs to be able to allow 24 Mhz crystal as input >> Update the range accordingly in plla characteristics struct >> >> Signed-off-by: Eugen Hrist

Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-16 Thread Stephen Boyd
Quoting eugen.hris...@microchip.com (2019-09-10 23:39:20) > From: Eugen Hristev > > The PLL input range needs to be able to allow 24 Mhz crystal as input > Update the range accordingly in plla characteristics struct > > Signed-off-by: Eugen Hristev > --- Is there a Fixes: tag for this? Seems l

Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-12 Thread Eugen.Hristev
On 12.09.2019 14:06, Alexander Dahl wrote: > > Hello, > > out of curiosity: The SAMA5D27-SOM1-EK board has a 24 MHz crystal, that is > also what /sys/kernel/debug/clk/clk_summary says and the board runs without > obvious problems. What is this change improving in real practice then? > The bo

Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-12 Thread Alexander Dahl
Hello, out of curiosity: The SAMA5D27-SOM1-EK board has a 24 MHz crystal, that is also what /sys/kernel/debug/clk/clk_summary says and the board runs without obvious problems. What is this change improving in real practice then? Greets Alex Am Mittwoch, 11. September 2019, 06:39:20 CEST schri

Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-11 Thread Nicolas.Ferre
On 11/09/2019 at 08:39, Eugen Hristev - M18282 wrote: > From: Eugen Hristev > > The PLL input range needs to be able to allow 24 Mhz crystal as input > Update the range accordingly in plla characteristics struct > > Signed-off-by: Eugen Hristev Acked-by: Nicolas Ferre Thanks Eugen! Best rega

[PATCH] clk: at91: allow 24 Mhz clock as input for PLL

2019-09-10 Thread Eugen.Hristev
From: Eugen Hristev The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev --- drivers/clk/at91/sama5d2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/at91