Re: [linux-sunxi] [PATCH] bus: sunxi-rsb: Make interrupt handling more robust

2019-10-07 Thread Samuel Holland
On 10/7/19 10:19 AM, Chen-Yu Tsai wrote: > On Sun, Aug 25, 2019 at 1:50 AM Samuel Holland wrote: >> >> The RSB controller has two registers for controlling interrupt inputs: >> RSB_INTE, which has bits for each possible interrupt, and the global >> interrupt enable bit in RSB_CTRL. >> >> Currently

Re: [linux-sunxi] [PATCH] bus: sunxi-rsb: Make interrupt handling more robust

2019-10-07 Thread Maxime Ripard
Hi, On Mon, Oct 07, 2019 at 11:19:06PM +0800, Chen-Yu Tsai wrote: > On Sun, Aug 25, 2019 at 1:50 AM Samuel Holland wrote: > > The RSB controller has two registers for controlling interrupt inputs: > > RSB_INTE, which has bits for each possible interrupt, and the global > > interrupt enable bit in

Re: [linux-sunxi] [PATCH] bus: sunxi-rsb: Make interrupt handling more robust

2019-10-07 Thread Chen-Yu Tsai
On Sun, Aug 25, 2019 at 1:50 AM Samuel Holland wrote: > > The RSB controller has two registers for controlling interrupt inputs: > RSB_INTE, which has bits for each possible interrupt, and the global > interrupt enable bit in RSB_CTRL. > > Currently, we enable the bits in RSB_INTE before each tran

Re: [PATCH] bus: sunxi-rsb: Make interrupt handling more robust

2019-10-07 Thread Samuel Holland
Hello, On 8/24/19 12:50 PM, Samuel Holland wrote: > The RSB controller has two registers for controlling interrupt inputs: > RSB_INTE, which has bits for each possible interrupt, and the global > interrupt enable bit in RSB_CTRL. > > Currently, we enable the bits in RSB_INTE before each transfer,

[PATCH] bus: sunxi-rsb: Make interrupt handling more robust

2019-08-24 Thread Samuel Holland
The RSB controller has two registers for controlling interrupt inputs: RSB_INTE, which has bits for each possible interrupt, and the global interrupt enable bit in RSB_CTRL. Currently, we enable the bits in RSB_INTE before each transfer, but this is unnecessary because we never disable them. Move