Hi,
On Tue, Aug 30, 2016 at 10:06 AM, Brian Norris wrote:
> On Tue, Aug 30, 2016 at 09:05:06AM +0200, Heiko Stuebner wrote:
>> Am Dienstag, 30. August 2016, 08:59:31 schrieb Elaine Zhang:
>> > On 08/30/2016 02:18 AM, Brian Norris wrote:
>> > > On Mon, Aug 29, 2016 at 11:11:24AM -0700, Doug Anders
On Tue, Aug 30, 2016 at 09:05:06AM +0200, Heiko Stuebner wrote:
> Am Dienstag, 30. August 2016, 08:59:31 schrieb Elaine Zhang:
> > On 08/30/2016 02:18 AM, Brian Norris wrote:
> > > On Mon, Aug 29, 2016 at 11:11:24AM -0700, Doug Anderson wrote:
> > >> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>
Hi Elaine,
Am Dienstag, 30. August 2016, 08:59:31 schrieb Elaine Zhang:
> On 08/30/2016 02:18 AM, Brian Norris wrote:
> > On Mon, Aug 29, 2016 at 11:11:24AM -0700, Doug Anderson wrote:
> >> On rk3399 we explicitly set ppll in the device tree to 67600. The
> >> ppll has one major child, pclk_p
On 08/30/2016 02:18 AM, Brian Norris wrote:
On Mon, Aug 29, 2016 at 11:11:24AM -0700, Doug Anderson wrote:
On rk3399 we explicitly set ppll in the device tree to 67600. The
ppll has one major child, pclk_pmu_src, that is the parent of lots of
other clocks. Right now nobody is setting tha
On Mon, Aug 29, 2016 at 11:11:24AM -0700, Doug Anderson wrote:
> On rk3399 we explicitly set ppll in the device tree to 67600. The
> ppll has one major child, pclk_pmu_src, that is the parent of lots of
> other clocks. Right now nobody is setting that clock rate and we're
> relying on the div
On rk3399 we explicitly set ppll in the device tree to 67600. The
ppll has one major child, pclk_pmu_src, that is the parent of lots of
other clocks. Right now nobody is setting that clock rate and we're
relying on the divider to just happen to be something sane. Let's be
explicit in our req
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