Dear Sebastian,
On Thu, 7 Jul 2016 19:10:26 +0200 Sebastian Hesselbarth wrote:
> On 07.07.2016 07:48, Jisheng Zhang wrote:
> > On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
> >> On 16.06.2016 10:40, Jisheng Zhang wrote:
> >>> This patch adds the L2 cache topology for berlin4c
On 07.07.2016 07:48, Jisheng Zhang wrote:
> On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
>> On 16.06.2016 10:40, Jisheng Zhang wrote:
>>> This patch adds the L2 cache topology for berlin4ct which has 1MB L2
>>> cache.
>>>
>>> Signed-off-by: Jisheng Zhang
>>> ---
>>> arch/arm64/b
Dear Sebastian,
On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
> On 16.06.2016 10:40, Jisheng Zhang wrote:
> > This patch adds the L2 cache topology for berlin4ct which has 1MB L2
> > cache.
> >
> > Signed-off-by: Jisheng Zhang
> > ---
> > arch/arm64/boot/dts/marvell/berlin4ct.
On 16.06.2016 10:40, Jisheng Zhang wrote:
> This patch adds the L2 cache topology for berlin4ct which has 1MB L2
> cache.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marv
This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.
Signed-off-by: Jisheng Zhang
---
arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
b/arch/arm64/boot/dts/marvell/berlin4ct.
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