Hi Jacopo,
On Thu, Oct 5, 2017 at 9:48 AM, jacopo mondi wrote:
> On Wed, Oct 04, 2017 at 05:54:46PM +0200, Geert Uytterhoeven wrote:
>> On Wed, Oct 4, 2017 at 5:40 PM, Jacopo Mondi
>> wrote:
>> > The system clock described by extal_clk is reported to have a frequency
>> > of 13.333 Mhz and is c
Hi Geert
On Wed, Oct 04, 2017 at 05:54:46PM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Wed, Oct 4, 2017 at 5:40 PM, Jacopo Mondi
> wrote:
> > The system clock described by extal_clk is reported to have a frequency
> > of 13.333 Mhz and is correctly described by gr-peach device tree.
>
Hi Jacopo,
On Wed, Oct 4, 2017 at 5:40 PM, Jacopo Mondi wrote:
> The system clock described by extal_clk is reported to have a frequency
> of 13.333 Mhz and is correctly described by gr-peach device tree.
>
> However, when enabling a RIIC device the following error is reported by
> drivers/i2c/bu
The system clock described by extal_clk is reported to have a frequency
of 13.333 Mhz and is correctly described by gr-peach device tree.
However, when enabling a RIIC device the following error is reported by
drivers/i2c/busses/i2c-riic.c
"invalid parent clk (2500). Must be 33325000Hz"
As R
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