On 10/17/2017 02:58 AM, Christoph Hellwig wrote:
> On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
>> From: Radha Mohan Chintakuntla
>>
>> This patch adds support for Cavium's fifth generation SATA controller.
>> It is an on-chip controller and complies with AHCI 1.3.1. A
On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
> From: Radha Mohan Chintakuntla
>
> This patch adds support for Cavium's fifth generation SATA controller.
> It is an on-chip controller and complies with AHCI 1.3.1. As the
> controller uses 64-bit addresses it cannot use
On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
> From: Radha Mohan Chintakuntla
>
> This patch adds support for Cavium's fifth generation SATA controller.
> It is an on-chip controller and complies with AHCI 1.3.1. As the
> controller uses 64-bit addresses it cannot use
From: Radha Mohan Chintakuntla
This patch adds support for Cavium's fifth generation SATA controller.
It is an on-chip controller and complies with AHCI 1.3.1. As the
controller uses 64-bit addresses it cannot use the standard AHCI BAR5
and so uses BAR4.
Signed-off-by: Radha Mohan Chintakuntla
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