Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-31 Thread James Hogan
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote: > Use 64-bit accesses for 64-bit floating-point general registers with > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > access"), whic

Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-24 Thread Paul Burton
Hi Maciej, On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote: > Use 64-bit accesses for 64-bit floating-point general registers with > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > ac

Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-24 Thread Maciej W. Rozycki
On Thu, 24 May 2018, James Hogan wrote: > > Use 64-bit accesses for 64-bit floating-point general registers with > > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > > access"), which inadvertently sw

Re: [PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-24 Thread James Hogan
On Wed, May 16, 2018 at 04:39:58PM +0100, Maciej W. Rozycki wrote: > Use 64-bit accesses for 64-bit floating-point general registers with > PTRACE_PEEKUSR, removing the truncation of their upper halves in the > FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context > access"), whic

[PATCH] MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

2018-05-16 Thread Maciej W. Rozycki
Use 64-bit accesses for 64-bit floating-point general registers with PTRACE_PEEKUSR, removing the truncation of their upper halves in the FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context access"), which inadvertently switched them to using 32-bit accesses. The PTRACE_POKEUSR