Re: [PATCH] Decouple CFG and IO in Designware PCIe Driver

2016-06-28 Thread Jingoo Han
On Monday, June 27, 2016 1:38 PM, Pratyush Anand wrote: > > On Wed, Jun 22, 2016 at 1:54 PM, dongbo (E) wrote: > > From: Dong Bo > > > > In designware PCIe driver, the iatu0 is used for both CFG and IO accesses. > > When PCIe sends CFGs to peripherals (e.g. lspci), > > iatu0 frequently switches

Re: [PATCH] Decouple CFG and IO in Designware PCIe Driver

2016-06-27 Thread Pratyush Anand
On Mon, Jun 27, 2016 at 6:38 PM, dongbo (E) wrote: > Hi, all. > > How about exchanging the assignments of `MEMORYs' and `CFGs/IOs'? > In other words, assign MEMEORYs to iatu0, CFGs and IOs to iatu1. > > Once the iatu0 is initialized to MEMORY accesses, its BASE_ADDR, > LIMIT and TYPE is fixed. MEM

Re: [PATCH] Decouple CFG and IO in Designware PCIe Driver

2016-06-27 Thread dongbo (E)
Hi, all. How about exchanging the assignments of `MEMORYs' and `CFGs/IOs'? In other words, assign MEMEORYs to iatu0, CFGs and IOs to iatu1. Once the iatu0 is initialized to MEMORY accesses, its BASE_ADDR, LIMIT and TYPE is fixed. MEMORYs match with iatu0 at first, so they will never being treated

Re: [PATCH] Decouple CFG and IO in Designware PCIe Driver

2016-06-26 Thread Pratyush Anand
On Wed, Jun 22, 2016 at 1:54 PM, dongbo (E) wrote: > From: Dong Bo > > In designware PCIe driver, the iatu0 is used for both CFG and IO accesses. > When PCIe sends CFGs to peripherals (e.g. lspci), > iatu0 frequently switches between CFG and IO alternatively. > > If the LIMIT of MEMORY is a value

[PATCH] Decouple CFG and IO in Designware PCIe Driver

2016-06-22 Thread dongbo (E)
From: Dong Bo In designware PCIe driver, the iatu0 is used for both CFG and IO accesses. When PCIe sends CFGs to peripherals (e.g. lspci), iatu0 frequently switches between CFG and IO alternatively. If the LIMIT of MEMORY is a value between CFGs BASE_ADDR and IOs LIMIT, this probably results in