On 15/06/16 16:36, Vladimir Murzin wrote:
> On 13/06/16 15:12, Alexandre TORGUE wrote:
>> According to ARM AN321 (section 4.12):
>>
>> "If the vector table is in writable memory such as SRAM, either relocated
>> by VTOR or a device dependent memory remapping mechanism, then
>> architecturally a mem
On 13/06/16 15:12, Alexandre TORGUE wrote:
> According to ARM AN321 (section 4.12):
>
> "If the vector table is in writable memory such as SRAM, either relocated
> by VTOR or a device dependent memory remapping mechanism, then
> architecturally a memory barrier instruction is required after the ve
According to ARM AN321 (section 4.12):
"If the vector table is in writable memory such as SRAM, either relocated
by VTOR or a device dependent memory remapping mechanism, then
architecturally a memory barrier instruction is required after the vector
table entry is updated, and if the exception is
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