Re: [PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-08-09 Thread sb...@codeaurora.org
On 08/09, Eugeniy Paltsev wrote: > On Thu, 2017-08-03 at 18:53 -0700, Stephen Boyd wrote: > > On 07/14, Eugeniy Paltsev wrote: > > > + /* input divider = reg.idiv + 1 */ > > > + idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> > > > CGU_PLL_CTRL_IDIV_SHIFT); > > > + /* fb divider = 2*(reg.fbdiv + 1) *

Re: [PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-08-09 Thread Eugeniy Paltsev
Hi Stephen,  thanks for respond, my comments are inlined below. On Thu, 2017-08-03 at 18:53 -0700, Stephen Boyd wrote: > On 07/14, Eugeniy Paltsev wrote: > [...] > > + dev_dbg(clk->dev, "write configurarion: 0x%x", val); >  > Or just use %#x to add the 0x part. Thanks, I don't know about this

Re: [PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-08-03 Thread Stephen Boyd
On 07/14, Eugeniy Paltsev wrote: > HSDKv1 boards manages it's clocks using various PLLs. These PLL has same s/it's/its/ s/has/have/ > dividers and corresponding control registers mapped to different addresses. > So we add one common driver for such PLLs. > > Each PLL on HSDK board consist of th

Re: [PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-07-27 Thread Stephen Boyd
On 07/27, Vineet Gupta wrote: > Hi Stephen, > > On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote: > >HSDKv1 boards manages it's clocks using various PLLs. These PLL has same > >dividers and corresponding control registers mapped to different addresses. > >So we add one common driver for such PLLs. >

Re: [PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-07-27 Thread Vineet Gupta
Hi Stephen, On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote: HSDKv1 boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consist of three divi

[PATCH] ARC: clk: introduce HSDKv1 pll driver

2017-07-14 Thread Eugeniy Paltsev
HSDKv1 boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed usin