On Mon, Jul 3, 2017 at 8:27 PM, Loc Ho wrote:
> Hi Rafael,
>
> >> >> The current SPCR code does not check the access width of the
> >> >> mmio, and
> >> >> uses a default of 8bit register accesses. This prevents
> >> >> devices that
> >> >> only do 16 or
Hi Rafael,
>> >> The current SPCR code does not check the access width of the
>> >> mmio, and
>> >> uses a default of 8bit register accesses. This prevents devices
>> >> that
>> >> only do 16 or 32bit register accesses from working. By simply
On Tue, Jun 20, 2017 at 11:27 PM, Jon Mason wrote:
> On Tue, Jun 20, 2017 at 2:33 PM, Loc Ho wrote:
>> Hi Jon,
>>
>>>
>>> >> >> The current SPCR code does not check the access width of the
>>> >> >> mmio, and
>>> >> >> uses a default of 8bit register accesses. This prevents devices
Hi Jon,
>>> >> >> The current SPCR code does not check the access width of the
>>> >> >> mmio, and
>>> >> >> uses a default of 8bit register accesses. This prevents devices
>>> >> >> that
>>> >> >> only do 16 or 32bit register accesses from working. By simply
>>> >> >>
On Tue, Jun 20, 2017 at 2:33 PM, Loc Ho wrote:
> Hi Jon,
>
>>
>> >> >> The current SPCR code does not check the access width of the mmio,
>> >> >> and
>> >> >> uses a default of 8bit register accesses. This prevents devices
>> >> >> that
>> >> >> only do 16 or 32bit register
Hi Jon,
>
> >> >> The current SPCR code does not check the access width of the mmio,
> >> >> and
> >> >> uses a default of 8bit register accesses. This prevents devices
> >> >> that
> >> >> only do 16 or 32bit register accesses from working. By simply
> >> >> checking
Hi Jon,
>> >> The current SPCR code does not check the access width of the mmio, and
>> >> uses a default of 8bit register accesses. This prevents devices that
>> >> only do 16 or 32bit register accesses from working. By simply
>> >> checking
>> >> this field and setting the
Sorry for top post. We would need to also need to handle other OEMs like HPE
m400. The set is limited but we want to key off the right ID. You could also
key off DMI data if it were later in boot. But probably too early at this point.
--
Computer Architect | Sent from my 64-bit #ARM Powered pho
On Mon, May 08, 2017 at 01:51:20PM -0700, Loc Ho wrote:
> Hi Jon,
>
> On Mon, May 8, 2017 at 1:34 PM, Jon Mason wrote:
> > On Mon, May 8, 2017 at 3:57 PM, Loc Ho wrote:
> >> Hi Jon,
> >>
>
> >> The current SPCR code does not check the access width of the mmio, and
> >> uses a defaul
Hi Jon,
On Mon, May 8, 2017 at 1:34 PM, Jon Mason wrote:
> On Mon, May 8, 2017 at 3:57 PM, Loc Ho wrote:
>> Hi Jon,
>>
>> The current SPCR code does not check the access width of the mmio, and
>> uses a default of 8bit register accesses. This prevents devices that
>> only do 16
On Mon, May 8, 2017 at 3:57 PM, Loc Ho wrote:
> Hi Jon,
>
>>>
> The current SPCR code does not check the access width of the mmio, and
> uses a default of 8bit register accesses. This prevents devices that
> only do 16 or 32bit register accesses from working. By simply checking
>
Hi Jon,
>>
The current SPCR code does not check the access width of the mmio, and
uses a default of 8bit register accesses. This prevents devices that
only do 16 or 32bit register accesses from working. By simply checking
this field and setting the mmio string appropriately,
On 05/08/2017 03:11 PM, Loc Ho wrote:
> Hi Jon,
>
>>> The current SPCR code does not check the access width of the mmio, and
>>> uses a default of 8bit register accesses. This prevents devices that
>>> only do 16 or 32bit register accesses from working. By simply checking
>>> this field and sett
Hi Jon,
>> The current SPCR code does not check the access width of the mmio, and
>> uses a default of 8bit register accesses. This prevents devices that
>> only do 16 or 32bit register accesses from working. By simply checking
>> this field and setting the mmio string appropriately, this issue
On 05/04/2017 11:05 AM, Jon Mason wrote:
> The current SPCR code does not check the access width of the mmio, and
> uses a default of 8bit register accesses. This prevents devices that
> only do 16 or 32bit register accesses from working. By simply checking
> this field and setting the mmio strin
On Thu, May 4, 2017 at 11:09 PM, Zheng, Lv wrote:
> Hi,
>
>> From: Jon Mason [mailto:jon.ma...@broadcom.com]
>> Sent: Thursday, May 4, 2017 11:06 PM
>> Subject: [PATCH] ACPI: SPCR: Use access width to determine mmio usage
>>
>> The current SPCR code does no
Hi,
> From: Jon Mason [mailto:jon.ma...@broadcom.com]
> Sent: Thursday, May 4, 2017 11:06 PM
> Subject: [PATCH] ACPI: SPCR: Use access width to determine mmio usage
>
> The current SPCR code does not check the access width of the mmio, and
> uses a default of 8bit regist
rown ;
>> Moore, Robert ; Zheng, Lv
>> Cc: linux-a...@vger.kernel.org; linux-kernel@vger.kernel.org;
>> de...@acpica.org; bcm-kernel-feedback-l...@broadcom.com
>> Subject: [PATCH] ACPI: SPCR: Use access width to determine mmio usage
>>
>> The current SPCR code does
7 8:06 AM
> To: Rafael Wysocki ; Len Brown ;
> Moore, Robert ; Zheng, Lv
> Cc: linux-a...@vger.kernel.org; linux-kernel@vger.kernel.org;
> de...@acpica.org; bcm-kernel-feedback-l...@broadcom.com
> Subject: [PATCH] ACPI: SPCR: Use access width to determine mmio usage
>
> The cu
The current SPCR code does not check the access width of the mmio, and
uses a default of 8bit register accesses. This prevents devices that
only do 16 or 32bit register accesses from working. By simply checking
this field and setting the mmio string appropriately, this issue can be
corrected. To
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