Re: [PATCH][v4] crypto: caam - Correct definition of registers in memory map

On Mon, Jun 23, 2014 at 03:08:28PM +0530, Ruchika Gupta wrote: > Some registers like SECVID, CHAVID, CHA Revision Number, > CTPR were defined as 64 bit resgisters. The IP provides > a DWT bit(Double word Transpose) to transpose the two words when > a double word register is accessed. However setti

[PATCH][v4] crypto: caam - Correct definition of registers in memory map

Some registers like SECVID, CHAVID, CHA Revision Number, CTPR were defined as 64 bit resgisters. The IP provides a DWT bit(Double word Transpose) to transpose the two words when a double word register is accessed. However setting this bit would also affect the operation of job descriptors as well