On 8/8/2018 1:50 PM, Stephen Boyd wrote:
Quoting Songjun Wu (2018-08-02 20:02:21)
From: Yixin Zhu
This driver provides PLL clock registration as well as various clock
branches, e.g. MUX clock, gate clock, divider clock and so on.
PLLs that provide clock to DDR, CPU and peripherals are
On 8/6/2018 11:18 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This patch adds binding documentation for grx500 clock controller.
Signed-off-by: YiXin Zhu
Signed-off-by: Songjun Wu
---
Changes in v2:
- Rewrite clock driver's dt-bi
On 8/6/2018 11:19 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote:
From: Yixin Zhu
This driver provides PLL clock registration as well as various clock
branches, e.g. MUX clock, gate clock, divider clock and so on.
PLLs that provide clock to DDR, CPU and
On 6/14/2018 10:09 PM, Rob Herring wrote:
On Thu, Jun 14, 2018 at 2:40 AM, yixin zhu wrote:
On 6/13/2018 6:37 AM, Rob Herring wrote:
On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
From: Yixin Zhu
PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
On 6/12/2018 7:23 PM, James Hogan wrote:
Hi,
Good to see this patch!
On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index ac7ad54f984f..bcd647060f3e 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbui
On 6/13/2018 6:37 AM, Rob Herring wrote:
On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
From: Yixin Zhu
PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
+-+
|--->| LCPLL3 0|--PCIe clk-->
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