Hi Eric,
On Fri, Feb 12, 2021 at 11:44 PM Auger Eric wrote:
>
> Hi Vivek,
>
> On 2/12/21 11:58 AM, Vivek Gautam wrote:
> > Update nested domain information required for stage1 page table.
>
> s/reuqired/required in the commit title
Oh! my bad.
> >
&
Update nested domain information required for stage1 page table.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm
ttps://lore.kernel.org/kvm/306e7dd2-9eb2-0ca3-6a93-7c9aa0821...@arm.com/
[5]
https://github.com/vivek-arm/linux/tree/5.11-rc3-nested-pgtbl-arm-smmuv3-virtio-iommu
Vivek Gautam (2):
iommu: Report domain nesting info for arm-smmu-v3
iommu: arm-smmu-v3: Report domain nesting info reuqired for st
Add a vendor specific structure for domain nesting info for
arm smmu-v3, and necessary info fields required to populate
stage1 page tables.
Signed-off-by: Vivek Gautam
---
include/uapi/linux/iommu.h | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff
aisd_bits data is required to prepare stage-1 tables for arm-smmu-v3.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc
ff-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/virtio-iommu.c
-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/virtio-iommu.c | 314
Fault type information can tell about a page request fault or
an unreceoverable fault, and further additions to fault reasons
and the related PASID information can help in handling faults
efficiently.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc
table format
Vivek Gautam (9):
iommu/arm-smmu-v3: Create a Context Descriptor library
iommu: Add a simple PASID table library
iommu/arm-smmu-v3: Update drivers to work with iommu-pasid-table
iommu/arm-smmu-v3: Update CD base address info for user-space
iommu/arm-smmu-v3: Set sync op from con
From: Jean-Philippe Brucker
Add the required UAPI defines for binding pasid tables in virtio-iommu.
This mode allows to hand stage-1 page tables over to the guest.
Signed-off-by: Jean-Philippe Brucker
[Vivek: Refactor to cleanup headers for invalidation]
Signed-off-by: Vivek Gautam
Cc: Joerg
x27;s needed with current iommu-pasid-table infrastructure.
Also updating uapi defines as required by latest changes]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc:
In preparation to add attach pasid table op, separate out the
existing attach request code to a separate method.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Add info about asid_bits and additional flags to table format
probing header.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc
-Philippe Brucker
[Vivek: Use a single "struct virtio_iommu_probe_table_format" rather
than separate structures for page table and pasid table format.
Also update commit message.]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Ro
Te change allows different consumers of arm-smmu-v3-cd-lib to set
their respective sync op for pasid entries.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi
n separate structures for page table and pasid table format.]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc:
Update arm-smmu-v3 context descriptor (CD) library driver to work
with iommu-pasid-table APIs. These APIs are then used in arm-smmu-v3
drivers to manage CD tables.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex
Update base address information in vendor pasid table info to pass that
to user-space for stage1 table management.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc
registering a vendor API that attaches
to these ops. The vendor APIs would eventually perform arch level
implementations for these PASID tables.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc
driver call such code.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/arm/arm-smmu
On Fri, Aug 23, 2019 at 12:03 PM Vivek Gautam
wrote:
>
> Add reset hook for sdm845 based platforms to turn off
> the wait-for-safe sequence.
>
> Understanding how wait-for-safe logic affects USB and UFS performance
> on MTP845 and DB845 boards:
>
> Qcom's implementati
On Wed, Sep 4, 2019 at 10:13 AM Bjorn Andersson
wrote:
>
> On Tue 27 Aug 04:01 PDT 2019, Vivek Gautam wrote:
>
> > On Fri, Aug 2, 2019 at 11:43 AM Vivek Gautam
> > wrote:
> > >
> > > On Thu, Jul 18, 2019 at 6:33 PM Vivek Gautam
> > > wrote:
>
On Fri, Aug 2, 2019 at 11:43 AM Vivek Gautam
wrote:
>
> On Thu, Jul 18, 2019 at 6:33 PM Vivek Gautam
> wrote:
> >
> > To better support future versions of llcc, consolidating the
> > driver to llcc-qcom driver file, and taking care of the dependencies.
> > v1
48576 count=300 conv=sync
300+0 records in
300+0 records out
314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s
real0m 1.03s
user0m 0.00s
sys 0m 0.54s
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu-impl.c | 27 ++-
1 file changed, 26 i
There are scnenarios where drivers are required to make a
scm call in atomic context, such as in one of the qcom's
arm-smmu-500 errata [1].
[1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/
tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n4842")
Signed-off-by: Vivek Gaut
/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9&id=8696005aaaf745de68f57793c1a534a34345c30a
[5] https://patchwork.kernel.org/patch/11096265/
[6] https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/
Vivek Gautam (3):
firmware: qcom_scm-64: Add atomic version of qcom_scm_call
firmware/qcom_scm: Ad
Qcom's smmu-500 needs to toggle wait-for-safe sequence to
handle TLB invalidation sync's.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
driver
On Tue, Aug 6, 2019 at 3:56 AM Bjorn Andersson
wrote:
>
> On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote:
>
> > Indicate on MTP SDM845 that firmware implements handler to
> > TLB invalidate erratum SCM call where SAFE sequence is toggled
> > to achieve optimum perfo
Hi Bjorn,
On Wed, Jul 10, 2019 at 5:09 PM Vivek Gautam
wrote:
>
> From: Sai Prakash Ranjan
>
> Last level cache (aka. system cache) controller provides control
> over the last level cache present on SDM845. This cache lies after
> the memory noc, right before the DDR.
>
m_qmp_phy_probe(struct platform_device
> *pdev)
> dev_err(qmp->dev,
> "failed to register pipe clock source\n");
> pm_runtime_disable(dev);
> + of_node_put(child);
Nice find. Thanks for the pat
On Thu, Jul 18, 2019 at 6:33 PM Vivek Gautam
wrote:
>
> To better support future versions of llcc, consolidating the
> driver to llcc-qcom driver file, and taking care of the dependencies.
> v1 series is availale at:
> https://lore.kernel.org/patchwork/patch/1099573/
>
For QUP IP versions 2.5 and above the oversampling rate is halved
from 32 to 16. Update this rate after reading hardware version
register, so that the clock divider value is correctly set to
achieve required baud rate.
Signed-off-by: Vivek Gautam
---
drivers/tty/serial/qcom_geni_serial.c | 15
The cleaning up was done without changing the driver file name
to ensure a cleaner bisect. Change the file name now to facilitate
making the driver generic in subsequent patch.
Signed-off-by: Vivek Gautam
---
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/{llcc-slice.c
A single file should suffice the need to program the llcc for
various platforms. Get rid of sdm845 specific driver file to
make way for a more generic driver.
Signed-off-by: Vivek Gautam
---
drivers/soc/qcom/Kconfig | 14 ++
drivers/soc/qcom/Makefile | 1 -
drivers/soc
This makes way for adding future llcc versions.
Also pull out the llcc-qcom specific definitions from includes.
Includes path now contains the only definitions that are
to be exposed to other subsystems.
Signed-off-by: Vivek Gautam
---
drivers/soc/qcom/llcc-qcom.c | 137
tform driver rather using a single
driver file now - llcc-qcom.
* Removed SCT_ENTRY macro.
* Moved few structure definitions from include/linux path to llcc-qcom
driver as they are not exposed to other subsystems.
Vivek Gautam (3):
soc: qcom: llcc cleanup to get rid of sdm845 specific driver
Hi Bjorn,
Thanks for the review.
On Thu, Jul 11, 2019 at 9:29 PM Bjorn Andersson
wrote:
>
> On Thu 11 Jul 04:03 PDT 2019, Vivek Gautam wrote:
>
> > - Remove 'sdm845' from names, and use 'plat' instead.
> > - Move SCT_ENTRY macro to header file.
> >
On Thu, Jul 11, 2019 at 9:19 PM Bjorn Andersson
wrote:
>
> On Thu 11 Jul 04:03 PDT 2019, Vivek Gautam wrote:
>
> > To avoid adding files for each future supported SoCs rename
> > the file to a generic name - llcc-plat, so that llcc configuration
> > tables for other So
- Remove 'sdm845' from names, and use 'plat' instead.
- Move SCT_ENTRY macro to header file.
- Create a new config structure to asssign to of-match-data.
Signed-off-by: Vivek Gautam
---
drivers/soc/qcom/llcc-plat.c | 77 --
include
To avoid adding files for each future supported SoCs rename
the file to a generic name - llcc-plat, so that llcc configuration
tables for other SoCs can be added in the same driver.
Signed-off-by: Vivek Gautam
---
drivers/soc/qcom/Kconfig| 10 +-
drivers/soc/qcom
From: Sai Prakash Ranjan
Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/sdm845
On Wed, Jun 26, 2019 at 8:18 PM Will Deacon wrote:
>
> On Wed, Jun 26, 2019 at 12:03:02PM +0530, Vivek Gautam wrote:
> > On Tue, Jun 25, 2019 at 7:09 PM Will Deacon wrote:
> > >
> > > On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote:
> > >
On Wed, Jun 19, 2019 at 5:46 AM Bjorn Andersson
wrote:
>
> Node names shouldn't include a vendor prefix and should whenever
> possible use a generic identifier. Resolve this by renaming the smmu
> nodes "iommu".
The bindings too say so :)
Reviewed-by: Vivek Gautam
Hi Marc,
On 6/13/2019 5:02 PM, Marc Gonzalez wrote:
readl_poll_timeout() calls usleep_range() to sleep between reads.
usleep_range() doesn't work efficiently for tiny values.
Raise the polling delay in qcom_qmp_phy_enable() to bring it in line
with the delay in qcom_qmp_phy_com_init().
Signed-
On 6/11/2019 4:51 AM, Stephen Boyd wrote:
Quoting Vivek Gautam (2019-06-06 04:17:16)
Hi Stephen,
On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
Quoting Vivek Gautam (2019-06-04 21:55:26)
Cheza will throw faults for anything that is programmed with TZ on mtp
as all of that should be
ce.codeaurora.org/quic/la/kernel/msm-4.9/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9&id=da765c6c75266b38191b38ef086274943f353ea7
[4]
https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9&id=8696005aaaf745de68f577
Qcom's smmu-500 needs to toggle wait-for-safe logic to
handle TLB invalidations.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
drivers/firmware/qcom_scm
Hi Stephen,
On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
>
> Quoting Vivek Gautam (2019-06-04 21:55:26)
> > On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd wrote:
> > >
> > > Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > > > On Tue
e mapping used for the splash screen
> framebuffer, which causes the board to reboot. This can be worked around
> using:
>
> fastboot oem select-display-panel none
This works well with your SMR handoff RFC series too?
>
> Signed-off-by: Bjorn Andersson
> ---
Patch looks go
Looks good to me and work well too with a wip lab-ibb driver change.
Reviewed-by: Vivek Gautam
Tested-by: Vivek Gautam
> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 79 +
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845
On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd wrote:
>
> Quoting Bjorn Andersson (2019-06-04 15:37:00)
> > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> >
> > > The SMMU that sits in front of the QUP needs to be programmed properly
> > > so that the i2c geni driver can allocate DMA descriptors
On Mon, Jun 3, 2019 at 4:14 PM Rob Clark wrote:
>
> On Mon, Jun 3, 2019 at 12:57 AM Vivek Gautam
> wrote:
> >
> >
> >
> > On 6/3/2019 11:50 AM, Tomasz Figa wrote:
> > > On Mon, Jun 3, 2019 at 4:40 AM Rob Clark wrote:
> > >> On Fri, May 10, 2
On 5/28/2019 2:13 PM, Marc Gonzalez wrote:
On 27/05/2019 12:26, Vivek Gautam wrote:
MTP SDM845 panel seems to need additional delay to bring panel
to a workable state. Running modetest without this change displays
blurry artifacts.
Signed-off-by: Vivek Gautam
---
drivers/gpu/drm/panel
For "qcom,msm8998-qmp-ufs-phy": no resets are listed.
> > + For "qcom,msm8998-qmp-pcie-phy" must contain:
> > + "phy", "common", "cfg".
> > For "qcom,sdm845-qmp-usb3-phy" must contain:
> > "phy", "common".
> > For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
>
> Please send the dt binding in a separate patch.
>
> Thanks
> Kishon
Thanks for the patch. Besides above comments from Kishon it looks good.
Reviewed-by: Vivek Gautam
Best regards
Vivek
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Hi Doug,
On Thu, Feb 28, 2019 at 2:34 AM Doug Anderson wrote:
>
> Hi,
>
> On Tue, Feb 26, 2019 at 3:54 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Tue, Feb 5, 2019 at 9:13 PM Bjorn Andersson
> > wrote:
> > >
> > > From: Sibi Sankar
> > >
> > > This patch adds Q6V5 MSS remoteproc node for S
On Tue, Jan 29, 2019 at 8:34 PM Ard Biesheuvel
wrote:
>
> (+ Bjorn)
>
> On Mon, 28 Jan 2019 at 12:27, Vivek Gautam
> wrote:
> >
> > Hi Ard,
> >
> > On Thu, Jan 24, 2019 at 1:25 PM Ard Biesheuvel
> > wrote:
> > >
> > > On Thu, 24 Ja
Hi Will,
On Tue, Jan 22, 2019 at 11:14 AM Will Deacon wrote:
>
> On Mon, Jan 21, 2019 at 11:35:30AM +0530, Vivek Gautam wrote:
> > On Sun, Jan 20, 2019 at 5:31 AM Will Deacon wrote:
> > > On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote:
> > > > Ad
On Mon, Jan 21, 2019 at 6:43 PM Robin Murphy wrote:
>
> On 17/01/2019 09:27, Vivek Gautam wrote:
> > From Robin's comment [1] about touching TCR configurations -
> >
> > "TBH if we're going to touch the TCR attributes at all then we should
> > probab
Hi Ard,
On Thu, Jan 24, 2019 at 1:25 PM Ard Biesheuvel
wrote:
>
> On Thu, 24 Jan 2019 at 07:58, Vivek Gautam
> wrote:
> >
> > On Mon, Jan 21, 2019 at 7:55 PM Ard Biesheuvel
> > wrote:
> > >
> > > On Mon, 21 Jan 2019 at 14:56, Robin Murphy wr
10:50, Ard Biesheuvel wrote:
> > >>> On Mon, 21 Jan 2019 at 11:17, Vivek Gautam
> > >>> wrote:
> > >>>>
> > >>>> Hi,
> > >>>>
> > >>>>
> > >>>> On Mon, Jan 21, 2019 at 12:56
On Mon, Jan 21, 2019 at 7:23 PM Robin Murphy wrote:
>
> On 21/01/2019 05:53, Vivek Gautam wrote:
> > A number of arm_smmu_domain's attributes can be assigned based
> > on the iommu domains's attributes. These local attributes better
> > be managed by a bitmap.
&g
On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
SDM845 has ETMv4.2 and can use the existing etm4x driver.
But the current etm driver checks only for ETMv4.0 and
errors out for other etm4x versions. This patch adds this
missing support to enable SoC's with ETMv4x to use same
driver by checking o
Hi,
On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
wrote:
>
> On Mon, 21 Jan 2019 at 06:54, Vivek Gautam
> wrote:
> >
> > Qualcomm SoCs have an additional level of cache called as
> > System cache, aka. Last level cache (LLC). This cache sits right
> > befor
Hi Will,
On Sun, Jan 20, 2019 at 5:31 AM Will Deacon wrote:
>
> On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote:
> > Adding a device tree option for arm smmu to enable non-cacheable
> > memory for page tables.
> > We already enable a smmu feature fo
o use system cache.
Signed-off-by: Vivek Gautam
---
drivers/iommu/io-pgtable-arm.c | 15 +--
drivers/iommu/io-pgtable.h | 4
include/linux/iommu.h | 2 ++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iom
A number of arm_smmu_domain's attributes can be assigned based
on the iommu domains's attributes. These local attributes better
be managed by a bitmap.
So remove boolean flags and move to a 32-bit bitmap, and enable
each bits separtely.
Signed-off-by: Vivek Gautam
---
drivers/iommu/
602
[4] https://lore.kernel.org/patchwork/cover/1032938/
Vivek Gautam (3):
iommu/arm-smmu: Move to bitmap for arm_smmu_domain atrributes
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add support to use system cache
drivers/iommu/arm-smmu
required memory attributes
to use system cache for buffers and page tables.
This change adds the support for iommu domain attributes and the
interaction with io page table driver.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu.c | 20 +++-
1 file changed, 19 insertions
.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index af18a7e7f917..7ebbcf1b2eb3 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -188,6 +188,7 @@ struct
-cacheable page tables for all masters
sitting on SMMU. Should this control be available per smmu_domain
as each master may have a different perf requirement?
Enabling this for the entire SMMU may not be desirable for all
masters.
[1] https://lore.kernel.org/patchwork/patch/1020906/
Vivek Gautam (2
7;t force
anybody _not_ using dma-coherent smmu to have non-cacheable page table
mappings.
Having another quirk flag can help in having non-cacheable memory for
page tables once and for all.
[1] https://lore.kernel.org/patchwork/patch/1020906/
Signed-off-by: Vivek Gautam
---
dr
PHY suspend enabled.
> Fix this by using quirks to disable USB2 PHY LPM/suspend and
> dwc3 core already takes care of explicitly suspending PHY
> during suspend if quirks are specified.
>
> Signed-off-by: Manu Gautam
> ---
This works well for db820c [1].
Tested-by: Vivek Gautam
After mapping a sg list the we should use sg_dma_address() and
sg_dma_len() macros to access sg->address and sg->length. Fix
the same for sg->length in drm_prime_sg_to_page_addr_arrays().
Signed-off-by: Vivek Gautam
---
Changes since v1:
- Fixed compilation error: replaced sg_dma_leng
please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Vivek-Gautam/drm-prime-Use-sg_dma_len-macro-to-get-sg-s-length/20190107-181350
> config: x86_64-randconfig-x013-201901 (attached as .config)
> compiler: gcc-7 (Debian 7.3.0-
After mapping a sg list we should use sg_dma_address(), and
sg_dma_len() macros to access sg->address and sg->length. Fix
the same for sg->length in drm_prime_sg_to_page_addr_arrays().
Signed-off-by: Vivek Gautam
---
This came while debugging one dmabuf import issue that we are seeing
Hi Robin,
On Fri, Dec 7, 2018 at 2:54 PM Vivek Gautam wrote:
>
> Hi Robin,
>
> On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
> >
> > On 04/12/2018 11:01, Vivek Gautam wrote:
> > > Qualcomm SoCs have an additional level of cache called as
> > >
On Thu, Dec 13, 2018 at 9:20 AM Tomasz Figa wrote:
>
> On Fri, Dec 7, 2018 at 6:25 PM Vivek Gautam
> wrote:
> >
> > Hi Robin,
> >
> > On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
> > >
> > > On 04/12/2018 11:01, Vivek Gautam wrote:
>
eak; \
> - } \
> - if (sleep_us) \
> - usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
> - } \
> - (cond) ? 0 : -ETIMEDOUT; \
> -})
> +#include
>
> #define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
>
On Thu, Dec 13, 2018 at 4:16 PM Will Deacon wrote:
>
> On Thu, Dec 13, 2018 at 02:35:07PM +0530, Vivek Gautam wrote:
> > Qcom's implementation of arm,mmu-500 works well with current
> > arm-smmu driver implementation. Adding a soc specific compatible
> > along with a
Qcom's implementation of arm,mmu-500 works well with current
arm-smmu driver implementation. Adding a soc specific compatible
along with arm,mmu-500 makes the bindings future safe.
Signed-off-by: Vivek Gautam
Reviewed-by: Rob Herring
Cc: Will Deacon
---
Hi Joerg,
I am picking thi
From: Archit Taneja
Add device node for display smmu, aka. mdp_smmu.
Signed-off-by: Archit Taneja
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64
From: Jordan Crouse
Add device node for graphics smmu, aka. adreno_smmu.
Signed-off-by: Jordan Crouse
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch
The driver side patches are now pulled in [1]. So, we can now enable
these smmu's used by display and graphics.
This has been lying in my test trees [2] for a while, and work well with
display and gpu enabled on msm8996.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=fo
Hi Will,
On Fri, Oct 12, 2018 at 11:37 AM Vivek Gautam
wrote:
>
>
>
> On 10/12/2018 3:46 AM, Rob Herring wrote:
> > On Thu, 11 Oct 2018 15:19:29 +0530, Vivek Gautam wrote:
> >> Qcom's implementation of arm,mmu-500 works well with current
> >> arm-smmu dri
On 12/7/2018 3:38 PM, Stanimir Varbanov wrote:
Hi Vivek,
Thanks for the patch!
On 12/5/18 10:31 AM, Vivek Gautam wrote:
Turning on CONFIG_DMA_API_DEBUG_SG results in the following error:
[ 460.308650] [ cut here ]
[ 460.313490] qcom-venus aa0.video-codec: DMA
Hi Robin,
On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
>
> On 04/12/2018 11:01, Vivek Gautam wrote:
> > Qualcomm SoCs have an additional level of cache called as
> > System cache, aka. Last level cache (LLC). This cache sits right
> > before the DDR, and is tightly
t;rx2) {
> + dev_warn(dev,
> +"Underspecified device tree, falling back to
> legacy register regions\n");
> +
> + /* In the old version, pcs_misc is at index 3. */
> + qphy->pcs_misc = qphy-&g
ovider, np);
> + if (ret)
> + phy_pipe_clk_release_provider(np);
> +
> + return ret;
> }
>
> static const struct phy_ops qcom_qmp_phy_gen_ops = {
> --
> 2.18.1
>
Tested on db820c [1]
Tested-by: Vivek Gautam
[1] https://github.com/vivekgautam1/linux/tree/origin/v4.20-rc5/db820c
BRs
Vivek
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
lt;1>;
> ranges;
> @@ -851,6 +852,7 @@
> reg = <0x7410200 0x200>,
> <0x7410400 0x130>,
> <0x7410600 0x1a8>;
> +
Hi,
On Fri, Dec 7, 2018 at 10:15 AM Kishon Vijay Abraham I wrote:
>
> Vivek,
>
> On 04/12/18 6:07 PM, Vivek Gautam wrote:
> > Hi Kishon,
> >
> > On Tue, Dec 4, 2018 at 1:44 PM Kishon Vijay Abraham I wrote:
> >>
> >> Hi Andy Gross, David Brown,
On Tue, Oct 23, 2018 at 10:07 AM Can Guo wrote:
>
> This patch series adds support for UFS QMP PHY on SDM845 and the
> compatible string for it. This patch series depends on the current
> proposed QMP V3 USB3 UNI PHY support for sdm845 driver [1], on
> the DT bindings for the QMP V3 USB3 PHYs base
On Tue, Oct 23, 2018 at 10:06 AM Can Guo wrote:
>
> From: Dov Levenglick
>
> Enables core reset support. Add full initialization of the PHY and the
> controller before initializing UFS PHY and during link recovery.
>
> Signed-off-by: Dov Levenglick
> Signed-off-by: Amit Nischal
> Signed-off-by:
Hi Kishon,
On Tue, Dec 4, 2018 at 1:44 PM Kishon Vijay Abraham I wrote:
>
> Hi Andy Gross, David Brown, Vivek,
>
> On 30/11/18 3:43 AM, Evan Green wrote:
> > This series fixes the QMP PHY bindings, which had specified #clock-cells
> > in the parent node, and had set it to 1. Putting it in the par
3]
https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/?h=msm-4.9&id=d4c72c413ea27c43f60825193d4de9cb8ffd9602
Signed-off-by: Vivek Gautam
---
Changes since v1:
- Addressed Tomasz's comments for basing the change on
"NO_INNER_CACHE" concept for non-coherent I/O devi
qcom,smmu-v2 is an arm,smmu-v2 implementation with specific
clock and power requirements.
On msm8996, multiple cores, viz. mdss, video, etc. use this
smmu. On sdm845, this smmu is used with gpu.
Add bindings for the same.
Signed-off-by: Vivek Gautam
Reviewed-by: Rob Herring
Reviewed-by: Tomasz
-off-by: Vivek Gautam
Reviewed-by: Tomasz Figa
Tested-by: Srinivas Kandagatla
Reviewed-by: Robin Murphy
---
Changes since v18:
None.
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1917d214c4d9
Hi Tomasz, Jordan,
On 11/21/2018 9:18 AM, Tomasz Figa wrote:
Hi Jordan, Vivek,
On Wed, Nov 21, 2018 at 12:41 AM Jordan Crouse wrote:
On Tue, Nov 20, 2018 at 03:24:37PM +0530, Vivek Gautam wrote:
dma_map_sg() expects a DMA domain. However, the drm devices
have been traditionally using
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
> +<&mmcc SMMU_VFE_AXI_CLK>;
> + clock-names = "iface",
> + "bus";
> +
On Mon, Nov 19, 2018 at 12:29 PM Shawn Guo wrote:
>
> On Sat, Nov 17, 2018 at 09:13:38AM -0600, Rob Herring wrote:
>
> > > > > +- qcom,init-seq:
> > > > > +Value type:
> > > > > +Definition: Should contain a sequence of
> > > > > tuples to
> > > > > +program 'value' int
On 2018-10-25 11:46, Vivek Gautam wrote:
Hi Manu,
On 10/16/2018 12:52 PM, Manu Gautam wrote:
Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.
Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New d
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