On Tue, Mar 16, 2021 at 12:29:16PM +0100, Jan Kara wrote:
> On Thu 04-03-21 13:35:38, Sascha Hauer wrote:
> > Current quotactl syscall uses a path to a block device to specify the
> > filesystem to work on which makes it unsuitable for filesystems that
> > do not have a bloc
On Wed, Mar 10, 2021 at 10:54:05AM +0800, dillon min wrote:
> Hi Sascha,
>
> Thanks for reviewing.
>
> On Tue, Mar 9, 2021 at 8:18 PM Sascha Hauer wrote:
> >
> > On Tue, Mar 09, 2021 at 02:15:19PM +0800, dillon.min...@gmail.com wrote:
> > > From: dillon min
rity data)
> Minimum required ECC for block 0 if PROGRAM/
> ERASE cycles are less than 1000 1-bit ECC per 528 bytes
4-bit ECC is the minimum this chip requires. There's nothing wrong with
choosing a better ECC like the GPMI driver does by default.
It looks like you
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
Reviewed-by: Christoph Hellwig
hidden inodes
for quota metadata storage
- Drop unnecessary quotactl_cmd_onoff() check
Sascha Hauer (2):
quota: Add mountpath based quota support
quota: wire up quotactl_path
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/i
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 31 ---
man2/quotactl_path.2 | 1 +
2 files changed, 29 insertions(+), 3
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
Reviewed-by: Christoph Hellwig
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64
ecryptfs_decrypt_page() issues a warning "Error encrypting extent". This
should be "Error decrypting extent" instead.
Signed-off-by: Sascha Hauer
---
fs/ecryptfs/crypto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/ecryptfs/crypto.c b/fs/ecr
On Fri, Feb 12, 2021 at 11:05:05AM +0100, Jan Kara wrote:
> On Fri 12-02-21 09:38:35, Sascha Hauer wrote:
> > On Thu, Feb 11, 2021 at 03:38:13PM +, Christoph Hellwig wrote:
> > > > + if (!mountpoint)
> > > > + return -ENODEV;
> > &
if (!special) {
if (cmds == Q_SYNC)
return quota_sync_all(type);
return -ENODEV;
}
Should we fix this or is there userspace code that is confused by a changed
return value?
Sascha
--
Pengutronix e.K.
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
---
fs/quota/quota.c | 49
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h
With this quotactl_path() can
only do the Q_QUOTAON operation on filesystems which use hidden inodes
for quota metadata storage
- Drop unnecessary quotactl_cmd_onoff() check
Sascha Hauer (2):
quota: Add mountpath based quota support
quota: wire up quotactl_path
arch/alpha/kernel/syscalls/syscall.tbl
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 31 ---
man2/quotactl_path.2 | 1 +
2 files changed, 29 insertions(+), 3
hich will hopefully trigger them to tell us why reset_device
is wrong for them.
At least for a staging driver I find this procedure opportune.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
+ }
Normally you don't want to see this error message when -EPROBE_DEFER is
returned because that would mean the reset controller is not yet
available and the driver should probe later again. There is
dev_err_probe() now for exactly this usecase.
Sascha
--
Pengutronix e.K.
g the full UBIFS quota series here as it remains unchanged
and I'd like to get feedback to the new syscall first. For those interested
the most recent series can be found here: https://lwn.net/Articles/810463/
Sascha
Sascha Hauer (2):
quota: Add mountpath based quota support
quot
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
---
fs/quota/quota.c | 77
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 19 +--
man2/quotactl_path.2 | 1 +
2 files changed, 18 insertions(+), 2 deletions
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h
On Wed, Jan 27, 2021 at 12:12:20PM +0200, Abel Vesa wrote:
> On 21-01-26 15:30:17, Sascha Hauer wrote:
> > On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> > > On 21-01-26 12:51:05, Sascha Hauer wrote:
> > > > On Tue, Jan 26, 2021 at 01:21:36PM +0200, A
On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> On 21-01-26 12:51:05, Sascha Hauer wrote:
> > On Tue, Jan 26, 2021 at 01:21:36PM +0200, Abel Vesa wrote:
> > > Some clocks are already enabled in HW even before the kernel
> > > starts to boot. So, in order to
oader enabled clock with CLK_IGNORE_UNUSED flag
can effectively never be disabled because the prepare/enable count is 1
without any user. This is the behaviour we want to have with critical
clocks, but I don't think this is desired for clocks with the
CLK_IGNORE_UNUSED flag.
Sascha
--
Pengutronix
On Wed, Jan 20, 2021 at 06:14:21PM +0200, Abel Vesa wrote:
> On 21-01-20 16:50:01, Sascha Hauer wrote:
> > On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> > > On 21-01-20 16:13:05, Sascha Hauer wrote:
> > > > Hi Abel,
> > > >
> > &g
On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> On 21-01-20 16:13:05, Sascha Hauer wrote:
> > Hi Abel,
> >
> > On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> > > On 21-01-18 08:00:43, Adam Ford wrote:
> > > > On Mon
s patch, and
> > the clk_summary shows the clock is running at the proper speed.
> > Without this patch, the UART fails to re-parent, so I'm stuck at lower
> > speeds and that means choppy Bluetooth audio.
> >
> > The Kernel that NXP hosts on Code Aurora that they
/* only support dt */
> + if (!of_stdout)
> + return;
> +
> + do {
> + uart_clk = of_clk_get(of_stdout, i++);
of_clk_get() allocates memory and gets you a reference to the clock. You
have to release the clock with clk_put(). I think
Hi Adam,
On Mon, Dec 07, 2020 at 09:51:33AM -0600, Adam Ford wrote:
> On Sun, Dec 6, 2020 at 11:24 PM Sascha Hauer wrote:
> >
> > Hi Adam,
> >
> > On Fri, Dec 04, 2020 at 12:31:54PM -0600, Adam Ford wrote:
> > > The default clock source on i.MX8M Mini and Nano
RT. With of_clk_get(of_stdout, i) you
get the nth clock for one specific UART.
What you have to do here is: For each of imx_uart_clocks[] you have to
iterate over all clocks of the of_stdout node.
Sascha
> + if (IS_ERR(uart_clk)
Hz it only works when we are waiting for the bit to clear.
Signed-off-by: Sascha Hauer
---
I've already sent this in October without any reaction, this is just a
resend with +Cc Stephen Boyd and +Cc linux-kernel@vger.kernel.org
drivers/clk/clk-si5351.c | 13 ++---
1 file c
ot;ubifs: Add helper functions for authentication
> support")
> Signed-off-by: Wang ShaoBo
> ---
> fs/ubifs/auth.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Sascha Hauer
Sascha
>
> diff --git a/fs/ubifs/auth.c b/fs/ubifs/auth.c
> index b
> Signed-off-by: Wang ShaoBo
> ---
> fs/ubifs/super.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Prefix for this patch should be "ubifs:" rather than "bdi:". With this:
Reviewed-by: Sascha Hauer
Sascha
>
> diff --git a/fs/ubifs/super.c
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ||
> *
> 02c0 06 70 c0 a8 00 00 00 00 00 00 00 00 40 00 00 00 |.p..@...|
Note beginning from offset 0x2c0 we get some uninitialized data. Among
other things we saw systemd unit files there.
Sascha
--
Pengutronix e
ial case
> clk: imx: gate2: Keep the register writing in on place
> clk: imx: gate2: Check if clock is enabled against cgr_val
> clk: imx: gate2: Add cgr_mask for more flexible number of control bits
> clk: imx: gate2: Add locking in is_enabled op
For the series:
Reviewed-by: Sasch
On Wed, Oct 28, 2020 at 11:50:57AM +0200, Abel Vesa wrote:
> On 20-10-28 09:24:12, Sascha Hauer wrote:
> > Hi Abel,
> >
> > On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote:
> > > The clock is considered to be enabled only if the controlling bits
> >
; gate->bit_idx;
> + else
> + reg &= ~(gate->cgr_val << gate->bit_idx);
Shouldn't this be:
reg &= ~(3 << gate->bit_idx);
if (enable)
reg |= gate->cgr_v
On Fri, Oct 09, 2020 at 09:48:29AM +0200, Christian Eggers wrote:
> Hi Sascha,
>
> On Friday, 9 October 2020, 09:39:44 CEST, Sascha Hauer wrote:
> > On Fri, Oct 09, 2020 at 06:27:38AM +0200, Christian Eggers wrote:
> > > This reverts commit 525c9e5a32bd7951eae3f06d9d077fea
On Mon, Oct 12, 2020 at 12:59:34PM +0200, Christian Eggers wrote:
> Hi Sascha,
>
> On Friday, 9 October 2020, 09:39:44 CEST, Sascha Hauer wrote:
> > On Fri, Oct 09, 2020 at 06:27:38AM +0200, Christian Eggers wrote:
> > > This reverts commit 525c9e5a32bd7951eae3f06d9d077fea
not just fix it?
Normally the device should be brought to active state manually in probe
before pm_runtime takes over, then CONFIG_PM disabled doesn't hurt.
Using pm_runtime to put the device to active state initially has the
problem you describe.
Sascha
--
On Tue, Sep 29, 2020 at 08:45:29PM +0800, Zhihao Cheng wrote:
> Fix a memory leak after dumping authentication mount options in error
> handling branch.
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support"
cause memory leak if UBIFS has already been
> mounted with old authentication mount options.
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support")
Reviewed-by: Sascha Hauer
Sascha
> ---
> fs/ubifs/super.
On Tue, Sep 29, 2020 at 08:45:31PM +0800, Zhihao Cheng wrote:
> Release the authentication related resource in some error handling
> branches in mount_ubifs().
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support
On Mon, Sep 28, 2020 at 09:06:12PM +0200, Richard Weinberger wrote:
> When removing the last reference of an inode the size of an auth node
> is already part of write_len. So we must not call ubifs_add_auth_dirt().
> Call it only when needed.
>
> Cc:
> Cc: Sascha Hauer
&g
Hi Sasha,
On Mon, Sep 28, 2020 at 09:30:25PM -0400, Sasha Levin wrote:
> From: Sascha Hauer
>
> [ Upstream commit 530b5affc675ade5db4a03f04ed7cd66806c8a1a ]
>
> spi_unregister_controller() not only unregisters the controller, but
> also frees the controller. This will free th
xitcode=0x000b
> > [2.160061] SMP: stopping secondary CPUs
> > [2.163999] Kernel Offset: disabled
> > [2.167496] CPU features: 0x0040022,20006008
> > [2.171777] Memory Limit: none
> > [2.174840] ---[ end Kernel panic - not syncing: Attempted to
nst: gpmi_io
> +- const: gpmi_apb
> +- const: gpmi_bch
> +- const: gpmi_bch_apb
> +- const: per1_bch
This enforces this specific order of the clocks given in the dts. The
clock binding itself doesn&#x
On Fri, Aug 21, 2020 at 09:52:00AM +, Robin Gong wrote:
> On 2020/08/20 14:52 Sascha Hauer wrote:
> > On Wed, Aug 19, 2020 at 01:08:29PM +0200, Lars-Peter Clausen wrote:
> > > > For the first option, which is potentially more performant, we have
> > > > to le
fsl,imx8mp-ocotp
> + - const: syscon
> + - items:
> + # The devices are not really compatible with fsl,imx8mm-ocotp,
> however
> + # the code for getting SoC revision depends on fsl,imx8mm-ocotp
> compatible.
Shouldn't this be fixed? It seems strange t
On Mon, Aug 24, 2020 at 08:38:06AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Aug 24, 2020 at 07:24:46AM +0200, Sascha Hauer wrote:
> > On Sun, Aug 23, 2020 at 06:15:30PM +0200, Krzysztof Kozlowski wrote:
> > > The GPIO controller node can have gpio-ranges property. This fixe
The subject contains a "imx-pwm", presumably from the last patch.
Sascha
On Sun, Aug 23, 2020 at 06:15:35PM +0200, Krzysztof Kozlowski wrote:
> DTSes with new i.MX 8M SoCs introduce their own compatibles so add them
> to fix dtbs_check warnings like:
>
> arch/arm64/boo
> + - if:
> + properties:
> +compatible:
> + contains:
> +const: fsl,imx8mp-gpio
> +then:
> + properties:
> +gpio-ranges:
> + minItems: 1
> + maxItems: 2
Why do you limit t
From: Sven Schneider
This font is derived from lib/fonts/font_6x10.c and is useful for small
OLED displays
Signed-off-by: Sven Schneider
Signed-off-by: Sascha Hauer
---
Changes since v1:
- re-added lost Signed-off-by lines
- do not mode change include/linux/font.h to 0755
- Add SPDX tag
; would be nice as well so I can stop trying getting it in :)
Sascha
include/linux/font.h |4 +-
lib/fonts/Kconfig|7 +
lib/fonts/Makefile |1 +
lib/fonts/font_6x8.c | 2575 ++
lib/fonts/fonts.c|3 +
5 files changed, 2589 insert
lled from sdma_start_desc(). sdma_config_ownership() also must be
called later in sdma_start_desc(). 'direction' must be a member of
struct sdma_desc, not of struct sdma_channel.
Overall this sounds like a fair amount of work to do, but should be
feasible and IMO is a step in the rig
valid interface modes early so that
later in the driver we do not have to care for unexpected interface
modes.
Add back the test to let the driver bail out early on unhandled
interface modes.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 22 +++---
1 file
SolidRun Clearfog:
WARNING: CPU: 0 PID: 268 at drivers/net/ethernet/marvell/mvneta.c:3512
mvneta_start_dev+0x220/0x23c
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
On Tue, Jun 23, 2020 at 12:53:40AM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Jun 16, 2020 at 10:31:39AM +0200, Sascha Hauer wrote:
> > The MVNETA_SERDES_CFG register is only available on older SoCs like the
> > Armada XP. On newer SoCs like the Armada 38x the fiel
and aborting after failures is not
consistent.
The function trace_boot_add_kprobe_event now reports each failure and
stops adding probes immediately.
Cc: linux-ker...@i4.cs.fau.de
Co-developed-by: Maximilian Werner
Signed-off-by: Maximilian Werner
Signed-off-by: Sascha Ortmann
---
kernel/trac
e the function can only return one result to the
caller, the function returns now the last failure (or none, if
nothing fails).
Cc: linux-ker...@i4.cs.fau.de
Signed-off-by: Maximilian Werner
Signed-off-by: Sascha Ortmann
---
kernel/trace/trace_boot.c | 16 +++-
1 file changed, 11 inser
writing the correct magic value into
the MVNETA_SERDES_CFG register.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 9933eb4577d43
configured.
With this we no longer write to the MVNETA_SERDES_CFG on SoCs where it
doesn't exist.
Suggested-by: Russell King
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 80 +++
1 file changed, 44 insertions(+), 36 deletions(-)
diff --
Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > > > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > > > called DRSGMII. Depending on the Port MAC Control Register0 PortType
> > > > setting this seems to be either an overclocke
ected with 172.16.1.0 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0-10.0 sec 1.27 GBytes 1.09 Gbits/sec
Still not 2.5Gbps, but at least twice the data rate you get, plus my
board has to handle both ends of the link.
Sascha
--
Pengutronix e.K. |
On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Control Reg
differentiate the different
possibilities.
Fixes: da58a931f248f ("net: mvneta: Add support for 2500Mbps SGMII")
Signed-off-by: Sascha Hauer
---
Changes since v1:
- Add Fixes: tag
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Hi Andrew,
+Cc Maxime Chevallier
On Tue, Jun 09, 2020 at 03:28:48PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Co
Hi Andrew,
On Tue, Jun 09, 2020 at 03:12:16PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 02:55:35PM +0200, Sascha Hauer wrote:
> > On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> > > On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> >
differentiate the different
possibilities.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 51889770958d8..3b13048931412
On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a corresponding phy-mode
On Mon, Jun 08, 2020 at 05:08:01PM +0100, Russell King - ARM Linux admin wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a co
to a FPGA.
Signed-off-by: Sascha Hauer
---
.../devicetree/bindings/net/ethernet-controller.yaml | 1 +
drivers/net/ethernet/marvell/mvneta.c | 7 ++-
include/linux/phy.h| 3 +++
3 files changed, 10 insertions(+), 1 deletion(-)
NABLED(CONFIG_MTD_UBI_FASTMAP) &&
!ubi->fm_disabled && !ubi->fm_anchor &&
e->pnum < UBI_FM_MAX_START)
And I am not sure if the IS_ENABLED(CONFIG_MTD_UBI_FASTMAP) is necessary
at all because we do a ubi->fm_disabled = 1 wh
be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the
On Wed, May 13, 2020 at 08:52:39AM +, Robin Gong wrote:
> On 2020/05/13 16:48 Sascha Hauer wrote:
> > On Wed, May 13, 2020 at 08:38:26AM +, Robin Gong wrote:
> > > On 2020/05/13 Sascha Hauer wrote:
> > > > This patch is the one bisecting will end up with
On Wed, May 13, 2020 at 09:05:33AM +, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer wrote:d
> > > drivers/spi/spi-imx.c | 16
> > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-imx.c b/dr
On Wed, May 13, 2020 at 08:38:26AM +, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer wrote:
> > This patch is the one bisecting will end up with when somebody uses an older
> > SDMA firmware or the ROM scripts. It should have a better description what
> > happens and what
if (spi_imx->devtype_data->tx_glitch_fixed)
+ tx.dst_maxburst = spi_imx->wml;
+ else
+ tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
So with tx_glitch_fixed we end up with tx.dst_m
M scripts. It should have a better
description what happens and what should be done about it.
Sascha
>
> Signed-off-by: Robin Gong
> Acked-by: Mark Brown
> ---
> drivers/spi/spi-imx.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> dif
be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id
gt;event_id0 = 0;
> sdmac->event_id1 = 0;
> - sdmac->context_loaded = false;
>
> sdma_set_channel_priority(sdmac, 0);
I think this can safely be folded into the next patch which makes it
more clear what is happening.
Sascha
--
Pengutronix e.K.
In the subject: s/dupilicated/duplicated/
Sascha
On Tue, May 12, 2020 at 01:32:28AM +0800, Robin Gong wrote:
> Since sdma_transfer_init() will do sdma_load_context before any
> sdma transfer, no need once more in sdma_config_channel().
>
> Signed-off-by: Robin Gong
> Acked
);
> + dev_info(dev, "enable clock '%s'\n", clk_name);
> + }
There's devm_clk_get_optional() which you should use here.
the "name" passed to devm_clk_get_optional() should match the name of
the clock, you must specify it according
Positions of the entries in nv_port_info[] must be consistent to enum
nv_host_type. Ensure this by using the enum as array index directly.
Signed-off-by: Sascha Hauer
---
drivers/ata/sata_nv.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/ata
On Sun, May 03, 2020 at 11:46:27PM +0200, Pali Rohár wrote:
> On Monday 27 January 2020 12:24:28 Sascha Hauer wrote:
> > On Mon, Jan 27, 2020 at 12:16:30PM +0100, Pali Rohár wrote:
> > > On Monday 06 January 2020 09:16:05 Sascha Hauer wrote:
> > > > On Wed, Dec 25,
c_dma *dma;
> > > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > > + struct i2c_client *slave;
> > > +#endif /* CONFIG_I2C_SLAVE */
> >
> > Other drivers just do a "select I2C_SLAVE" in Kconfig to get rid of these
> > #ifs.
Received ACK */
Same here.
> + ctl |= I2CR_MTX;
> + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
> +
> + i2c_slave_event(i2c_imx->slave,
> I2C_SLAVE_READ_PROCESSED, &value);
> +
> +
On Tue, Jul 02, 2019 at 05:54:54PM +0100, Srinivas Kandagatla wrote:
> Hi Sascha,
>
> On 01/07/2019 09:06, Sascha Hauer wrote:
> > Hi Srinivas,
> >
> > On Tue, May 21, 2019 at 11:21:07AM +0200, Sascha Hauer wrote:
> > > On Tue, May 21, 2019 at 10:02:3
Hi Srinivas,
On Tue, May 21, 2019 at 11:21:07AM +0200, Sascha Hauer wrote:
> On Tue, May 21, 2019 at 10:02:32AM +0100, Srinivas Kandagatla wrote:
> >
> >
> > On 21/05/2019 09:56, Sascha Hauer wrote:
> > > . Are there any suggestions how to register the nvmem devic
Hi,
On Fri, Jun 14, 2019 at 09:23:48AM +0200, Sascha Hauer wrote:
> First two patches are a fix for the Marvell HCI driver which fails to
> properly upload the firmware. Third patch adds simple serdev support
> to the driver.
>
> Sascha
>
> Sascha Hauer (3):
> B
First two patches are a fix for the Marvell HCI driver which fails to
properly upload the firmware. Third patch adds simple serdev support
to the driver.
Sascha
Sascha Hauer (3):
Bluetooth: hci_ldisc: Add function to wait for characters to be sent
Bluetooth: hci_mrvl: Wait for final ack
final ack with the old baudrate give the hci
ldisc workqueue a chance to run before switching the baudrate. Without
this the final ack will never be received by the device and firmware
upload fails.
Signed-off-by: Sascha Hauer
---
drivers/bluetooth/hci_mrvl.c | 3 +++
1 file changed, 3 insertions
The hci UART line discipline sends its characters in a workqueue. Some
devices like the Marvell Bluetooth chips need to make sure that all
queued characters are sent before switching the baudrate. This adds
a function to synchronize with the workqueue.
Signed-off-by: Sascha Hauer
---
drivers
This adds serdev support to the Marvell hci uart driver. Only basic
serdev support, none of the fancier features like regulator or enable
GPIO support is added for now.
Signed-off-by: Sascha Hauer
---
.../bindings/net/marvell-bluetooth.txt| 25 +++
drivers/bluetooth/Kconfig
EDMA64_SSRT : EDMA_SSRT);
> + edma->regs.cdne = edma->membase + ((edma->version == v2) ?
> + EDMA64_CDNE : EDMA_CDNE);
> + edma->regs.intl = edma->membase + ((edma->version == v2) ?
> + EDMA6
edma_writel(fsl_edma, ~0, regs->intl);
> - ret = fsl_edma_irq_init(pdev, fsl_edma);
> +
> + if (fsl_edma->version == v3)
> + ret = fsl_edma2_irq_init(pdev, fsl_edma);
> + else
> + ret = fsl_edma_irq_init(pdev, fsl_edma);
...and this one
On Tue, May 21, 2019 at 10:02:32AM +0100, Srinivas Kandagatla wrote:
>
>
> On 21/05/2019 09:56, Sascha Hauer wrote:
> > . Are there any suggestions how to register the nvmem devices
> > with a different name?
>
> struct nvmem_config provides id field for this pu
to register the nvmem devices
with a different name?
Sascha
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Am
The Kernel has nice hexdump facilities, use them rather a homebrew
hexdump function.
Signed-off-by: Sascha Hauer
---
fs/ecryptfs/debug.c | 22 +++---
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a/fs/ecryptfs/debug.c b/fs/ecryptfs/debug.c
index 3d2bdf546ec6
ivider sits between the clock module and the
i2c module, but for sure it's not in the i2c module. I really suggest to
put this SoC specific into the SoC specific clock driver rather than
littering the i2c driver with it.
Sascha
>
> Now based on the what is the desired SCL value (100KHz
I2C_IPGCLK_WORD, rcw_reg);
> + if (rcw_reg & RCW_I2C_IPGCLK_MASK) {
> + pr_alert("Div by 2 Case Detected in RCW\n");
> + i2c_ipgclk_sel = 1;
> + } else {
> + pr_alert("Div by 4 Case Detec
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