From: Ondrej Jirman
The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
external USB3 pins of the SoC.
Add a device tree binding for the PHY.
Signed-off-by: Ondrej Jirman
---
.../phy/allwinner,sun50i-h6-usb3-phy.yaml | 47 +++
1 file changed, 47 insertions(+)
From: Icenowy Zheng
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Ondrej Jirman
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++
From: Icenowy Zheng
Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).
Add a driver for it.
The register operations in this driver is mainly extracted from the BSP
USB3 driver.
Signed-off-by: Ondrej Jirman
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
From: Ondrej Jirman
This series implements USB 3 support for Xunlong Orange Pi 3 board.
This is a re-hash of the Icenowy's earlier USB3 work[1] without code
that caused controversy previously. Orange Pi 3 board doesn't need vbus
supply to be dynamically enabled, so that code is not needed to sup
From: Ondrej Jirman
Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3
board has GL3510 USB 3.0 4-port hub connected to the SoC's USB 3.0
port. All four ports are exposed via USB3-A connectors. VBUS is
always on, since it's powered directly from DCIN (VCC-5V) and
not switchable.
From: Ondrej Jirman
Since 5.4-rc1, pwm_apply_state calls ->get_state after ->apply
if available, and this revealed an issue with integer precision
when calculating duty_cycle and period for the currently set
state in ->get_state callback.
This issue manifested in broken backlight on several Allw
From: Ondrej Jirman
Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that we can use
them.
Signed-off-by: Ondrej Jirman
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/a
From: Ondrej Jirman
The board contains AP6256 WiFi/BT module that has its bluetooth part
connected to SoC's UART1 port. Enable this port, and add node for the
bluetooth device.
Bluetooth part is named bcm4345c5.
You'll need a BCM4345C5.hcd firmware file that can be found in the
Xulongs's reposi
From: Ondrej Jirman
(Re-send for Maxime, with already applied patches dropped. Nothing new.)
This series implements bluetooth support for Xunlong Orange Pi 3 board.
The board uses AP6256 WiFi/BT 5.0 chip.
Summary of changes:
- add more delay to let initialize the chip
- let the kernel detect
From: Ondrej Jirman
Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that we can use
them.
Signed-off-by: Ondrej Jirman
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/a
From: Ondrej Jirman
Detect BCM4345C5 and load a corresponding firmware file.
Signed-off-by: Ondrej Jirman
---
Checkpatch reports a spurious error.
drivers/bluetooth/btbcm.c | 3 +++
drivers/bluetooth/hci_bcm.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/bluetooth/btbcm.c b
From: Ondrej Jirman
This is present in the AP6526 WiFi/Bluetooth 5.0 module.
Signed-off-by: Ondrej Jirman
---
Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
b/Documen
From: Ondrej Jirman
The board contains AP6256 WiFi/BT module that has its bluetooth part
connected to SoC's UART1 port. Enable this port, and add node for the
bluetooth device.
Bluetooth part is named bcm4345c5.
You'll need a BCM4345C5.hcd firmware file that can be found in the
Xulongs's reposi
From: Ondrej Jirman
Some supported devices need more time to come out of reset (eg.
BCM4345C5 in AP6256).
I don't have/found a datasheet, so the value was arrive at
experimentally with the Oprange Pi 3 board. Without increased delay,
I got intermittent failures during probe. This is a Bluetooth
From: Ondrej Jirman
(Resend to add missing lists, sorry for the noise.)
This series implements bluetooth support for Xunlong Orange Pi 3 board.
The board uses AP6256 WiFi/BT 5.0 chip.
Summary of changes:
- add more delay to let initialize the chip
- let the kernel detect firmware file path
-
From: Ondrej Jirman
Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called
bcm43356 and can be used with the brcmfmac driver. The module is powered by
the two always on regulators (not AXP805).
WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be
configured so t
From: Ondrej Jirman
RTC on H6 is mostly the same as on H5 and H3. It has slight differences
mostly in features that are not yet supported by this driver.
Some differences are already stated in the comments in existing code.
One other difference is that H6 has extra bit in LOSC_CTRL_REG, called
E
From: Ondrej Jirman
RTC on H6 is similar to the one on H5 SoC, but incompatible in small
details. See the driver for description of differences. For example
H6 RTC needs to enable the external low speed oscillator. Add new
compatible for this RTC.
Signed-off-by: Ondrej Jirman
---
.../bindings/
From: Ondrej Jirman
This patch adds RTC node and fixes the clock properties and nodes
to reflect the real clock tree.
The device nodes for the internal oscillator and osc32k are removed,
as these clocks are now provided by the RTC device. Clock references
are fixed accordingly, too.
Signed-off-
From: Ondrej Jirman
I went through the datasheets for H6 and H5, and compared the differences.
RTCs are largely similar, but not entirely compatible. Incompatibilities
are in details not yet implemented by the rtc driver though.
I also corrected the clock tree in H6 DTSI.
This patchset is neces
From: Ondrej Jirman
This is already supported by the driver, but is missing from the
bindings.
Signed-off-by: Ondrej Jirman
---
.../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml| 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/net/allwinner
From: Ondrej Jirman
We'll be adding further optional regulators, and this makes it clearer
what the regulator is for.
Signed-off-by: Ondrej Jirman
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 32 ++-
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers
From: Ondrej Jirman
This series implements ethernet support for Xunlong Orange Pi 3 board, by:
- making small cleanups of existing dwmac-sun8i code
- adding DT bindings docummentation
- adding support for phy-io-supply to dwmac-sun8i code
- adding DT configuration for Orange Pi 3 board
For some
From: Ondrej Jirman
Orange Pi 3 has two regulators that power the Realtek RTL8211E
PHY. According to the datasheet, both regulators need to be enabled
at the same time, or that "phy-io" should be enabled slightly earlier
than "phy" regulator.
RTL8211E/RTL8211EG datasheet says:
Note 4: 2.5V (o
From: Ondrej Jirman
Some PHYs require separate power supply for I/O pins in some modes
of operation. Add phy-io-supply property, to allow enabling this
power supply.
Signed-off-by: Ondrej Jirman
---
.../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml| 4
1 file changed, 4 inser
From: Ondrej Jirman
Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
to the phy datasheet, both regulators need to be enabled at the same time.
Add support for the second optional regulator, "phy-io", to the glue
driver.
Signed-off-by: Ondrej Jirman
---
.../net/ethern
From: Ondrej Jirman
Use devm_regulator_get instead of devm_regulator_get_optional and rely
on dummy supply. This avoids NULL checks before regulator_enable/disable
calls.
This path also improves error reporting, because we now report both
use of dummy supply and error during registration with mo
From: Icenowy Zheng
The PHY selection bit also exists on SoCs without an internal PHY; if it's
set to 1 (internal PHY, default value) then the MAC will not make use of
any PHY on such SoCs.
This problem appears when adapting for H6, which has no real internal PHY
(the "internal PHY" on H6 is not
From: Ondrej Jirman
Some Allwinner SoC using boards (Orange Pi 3 for example) need to enable
on-board voltage shifting logic for the DDC bus using a gpio to be able
to access DDC bus. Use ddc-en-gpios property on the hdmi-connector to
model this.
Add binding documentation for optional ddc-en-gpi
From: Ondrej Jirman
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
S
From: Ondrej Jirman
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
S
From: Chen-Yu Tsai
The A83T SoC has a camera sensor interface (known as CSI in Allwinner
lingo), which is similar to the one found on the A64 and H3. The only
difference seems to be that support of MIPI CSI through a connected
MIPI CSI-2 bridge.
Add a compatible string for this variant.
Signed-
From: Chen-Yu Tsai
The A83T SoC has a camera sensor interface (known as CSI in Allwinner
lingo), which is similar to the one found on the A64 and H3. The only
difference seems to be that support of MIPI CSI through a connected
MIPI CSI-2 bridge.
Add a device node for it, and pinctrl nodes for th
From: Ondrej Jirman
This is a re-send of Chen-Yu's A83T CSI patch series with review tags
applied and removed address/size cells from csi_in port. Already applied
patches from v1 were dropped.
The series is ready to be merged:
Patch 1 and 2 via sunxi tree
Patch 3 via media tree
v2:
- drop
From: Chen-Yu Tsai
The A83T SoC has a camera sensor interface (known as CSI in Allwinner
lingo), which is similar to the one found on the A64 and H3. The only
difference seems to be that support of MIPI CSI through a connected
MIPI CSI-2 bridge.
Add support for this variant.
Signed-off-by: Chen
From: Ondrej Jirman
This series adds some properties to prepare for passive cooling via
CPU frequency down-regulation, and fixes cpufreq for various CPU hotplug
situations.
#cooling-cells patch is not strictly necessary now, but now that SID
changes are soon to be merged, thermal sensor patches
From: Ondrej Jirman
TBS A711 tablet contains u-blox NEO-6M module connected to UART2.
Enable UART2 to gain access to the module from userspace.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/
From: Ondrej Jirman
This fixes an error from the refactoring of literals to mask preproccesor
definitions that was done during the 5.0 release cycle.
Found by debugging a broken voltage setup on Orange Pi One Plus.
Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks")
Signed-off-by:
From: Ondrej Jirman
This fixes another set of errors from the refactoring of literals
to mask preproccesor definitions.
Found by debugging a broken voltage setup on Orange Pi One Plus.
Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks")
Signed-off-by: Ondrej Jirman
---
This is a
From: Ondrej Jirman
When cedrus_hw_probe is called, v4l2_dev is not yet initialized.
Use dev_err instead.
Signed-off-by: Ondrej Jirman
---
.../staging/media/sunxi/cedrus/cedrus_hw.c| 28 +--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/med
From: Ondrej Jirman
When parallel bus is used and data-active is being parsed, incorrect
flags are cleared.
Clear the correct flag bits.
Fixes: e9be1b863e2c2948deb003df8edd9635b4611a8a (media: v4l: fwnode:
Use default parallel flags).
Signed-off-by: Ondrej Jirman
---
drivers/media/v4l2-core/
From: Ondrej Jirman
The actual hardware has 4 data lines. Use them.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 7a1b61
From: Ondrej Jirman
The reverted commit broke LVDS output on TBS A711 Tablet. That tablet
has simple-panel node that has fixed pixel clock-frequency that A83T
SoC used in the tablet can't generate exactly.
Requested rate is 5200 and rounded_rate is calculated as 51857142.
It's close enough f
From: Ondrej Jirman
Currently the exclusivity is enabled when the rate is set by
the mode setting functions. These functions are called by
mode_set_nofb callback of drm_crc_helper. Then exclusivity
is disabled when tcon is disabled by atomic_disable
callback.
What happens is that mode_set_nofb c
From: Ondrej Jirman
I noticed that with 4.16-rc1 LVDS output on A83T based TBS A711 tablet doesn't
work (there's output but it's garbled). I compared some older patches for LVDS
support with the mainlined ones and this change is missing from mainline Linux.
I don't know what the register does ex
From: Ondrej Jirman
Without this the AXP813 PMIC fails to probe on TBS A711.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
ind
From: Ondrej Jirman
Datasheet specified that parent MUX settings are at bits [10:8],
but current implementation specifies incorrect offset at [10:12].
Fix this.
Signed-off-by: Ondrej Jirman
---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
From: Ondrej Jirman
When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).
Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.
Signed-off-by: Ondrej Jirman
Tested-by: Lutz Sammer
From: Ondrej Jirman
This patch adds support for the sun8i thermal sensor on
Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman
---
v2:
- removed incorrect use of SID driver in sun8i_ths
- read calibration data directly from iomem
- better explanation for the thermal sensor driver
- dt documentati
From: Josef Gajdusek
This patch adds a driver for the THS clock which is present on the
Allwinner H3.
Signed-off-by: Josef Gajdusek
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-h3-ths.c
From: Ondrej Jirman
This patch adds the binding documentation for the
sy8106a regulator driver.
Signed-off-by: Ondrej Jirman
---
.../bindings/regulator/sy8106a-regulator.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644
Documentation/devicetree/bindin
From: Ondrej Jirman
PLL1 on H3 requires special factors application algorithm,
when the rate is changed. This algorithm was extracted
from the arisc code that handles frequency scaling
in the BSP kernel.
This algorithm is implemented by sun8i-h3-pll1-clk.
Signed-off-by: Ondrej Jirman
---
arch
From: Ondrej Jirman
Add label to the first cpu so that it can be referenced
from derived dts files.
Signed-off-by: Ondrej Jirman
---
v2
- move clocks/clock-latency to sun8i-h3.dtsi
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch
From: Ondrej Jirman
Use Xulong Orange Pi One GPIO based regulator for
passive cooling and thermal management.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-
From: Ondrej Jirman
PLL1 on H3 requires special factors application algorithm,
when the rate is changed. This algorithm was extracted
from the arisc code that handles frequency scaling
in the BSP kernel.
This commit adds optional apply function to
struct factors_data, that can implement non-triv
From: Ondrej Jirman
Xulong Orange Pi One uses GPIO based regulator that
switches between two voltages: 1.1V and 1.3V. The
regulator is controlled from the PL6 pin.
Signed-off-by: Ondrej Jirman
---
v2
- add missing pinctrl-names for gpio-regulator
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
From: Ondrej Jirman
This patch adds nodes for the thermal sensor driver and
the THS clock to the Allwinner sun8i-h3.dtsi file.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/su
From: Ondrej Jirman
Add sy8106a regulator to r_twi bus and enable the r_twi bus on
Orange Pi PC. This regulator controls the CPUX voltage.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/bo
From: Ondrej Jirman
H3 SoC contains I2C controller optionally available
on the PL0 and PL1 pins. This patch makes this controller
available.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3.dtsi | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff
From: Ondrej Jirman
Orange PI PC uses SY8106A regulator for fine grained CPUX voltage
regulation. Setup appropriate operating points for the board.
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 48 ++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts
From: Ondrej Jirman
SY8106A is I2C attached single output voltage regulator
made by Silergy.
Signed-off-by: Ondrej Jirman
---
v2
- added dt-bindings for the regulator
- changed to use of_device_id for probing
- added initialization failure checks
---
drivers/regulator/Kconfig | 8
From: Ondrej Jirman
This patch adds the binding documentation for the
sun8i_ths driver. This is a driver for thermal sensor
found in Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman
---
.../devicetree/bindings/thermal/sun8i-ths.txt | 26 ++
1 file changed, 26 insertions(
From: Ondrej Jirman
Orange PI PC uses SY8106A regulator for fine grained CPUX voltage
regulation. Setup appropriate operating points for the board.
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 50 ++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts
From: Josef Gajdusek
Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
Signed-off-by: Josef Gajdusek
---
arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index
From: Ondrej Jirman
Xulong Orange Pi One uses GPIO based regulator that
switches between two voltages: 1.1V and 1.3V. The
regulator is controlled from the PL6 pin.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 26 ++
1 file changed, 26 i
From: Ondrej Jirman
Add sy8106a regulator to r_twi bus on Orange Pi PC. This
regulator controls the CPUX voltage.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.d
From: Ondrej Jirman
Add label to the first cpu so that it can be referenced
from derived dts files.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.
From: Ondrej Jirman
Use Xulong Orange Pi One GPIO based regulator for
passive cooling and thermal management.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-
From: Ondrej Jirman
This patch adds nodes for the THS driver and the THS clock to
the Allwinner sun8i-h3.dtsi file.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3
From: Ondrej Jirman
Enable I2C controller where the SY8106A regulator for
CPUX voltage is attached on Orange Pi PC SBC.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
From: Ondrej Jirman
PLL1 on H3 requires special factors application algorithm,
when the rate is changed. This algorithm was extracted
from the arisc code that handles frequency scaling
in the BSP kernel.
This commit adds optional apply function to
struct factors_data, that can implement non-triv
From: Ondrej Jirman
SY8106A is I2C attached single output voltage regulator
made by Silergy.
Signed-off-by: Ondrej Jirman
---
drivers/regulator/Kconfig | 8 +-
drivers/regulator/Makefile| 2 +-
drivers/regulator/sy8106a-regulator.c | 153
From: Ondrej Jirman
H3 SoC contains I2C controller optionally available
on the PL0 and PL1 pins. This patch makes this controller
available.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-h3.dtsi | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff
From: Josef Gajdusek
This patch adds a driver for the THS clock which is present on the
Allwinner H3.
Signed-off-by: Josef Gajdusek
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-h3-ths.c
From: Ondrej Jirman
This patch adds the binding documentation for the sun8i_ths driver
Signed-off-by: Ondřej Jirman
---
.../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal
From: Ondrej Jirman
This patch adds support for the sun8i thermal sensor on
Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman
---
drivers/thermal/Kconfig | 7 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/sun8i_ths.c | 295
3 files chan
76 matches
Mail list logo
