Got it, thanks.
Regards
Bibo Mao
On 2024/10/22 下午5:45, Huacai Chen wrote:
On Tue, Oct 22, 2024 at 5:17 PM maobibo wrote:
Hi Huacai/Thomas,
Sorry for the ping message :(
Can this patch be applied int next RC version?
Queued for the next release.
Huacai
Regards
Bibo Mao
On 2024/10/2
Hi Huacai/Thomas,
Sorry for the ping message :(
Can this patch be applied int next RC version?
Regards
Bibo Mao
On 2024/10/2 下午9:42, Thomas Gleixner wrote:
On Wed, Sep 11 2024 at 17:11, Huacai Chen wrote:
Hi, Thomas,
On Fri, Aug 30, 2024 at 5:32 PM Bibo Mao wrote:
Interrupts can be route
Reviewed-by: Bibo Mao
On 2024/10/14 下午7:36, Thomas Weißschuh wrote:
QEMU for LoongArch does not yet support shutdown/restart through ACPI.
Use the pvpanic driver to enable shutdowns.
This requires 9.1.0 for shutdown support in pvpanic, but that is the
requirement of kunit on LoongArch anyways.
Hi Thomas,
Thanks for work it out on LoongArch.
Reviewed-by: Bibo Mao
On 2024/10/14 下午7:36, Thomas Weißschuh wrote:
Add a basic config to run kunit tests on LoongArch.
This requires QEMU 9.1.0 or later for the necessary direct kernel boot
support.
Signed-off-by: Thomas Weißschuh
---
tools
Huacai,
On 2024/8/28 下午10:27, Huacai Chen wrote:
Hi, Bibo,
On Fri, Aug 23, 2024 at 2:39 PM Bibo Mao wrote:
Interrupts can be routed to maximal four virtual CPUs with one HW
EIOINTC interrupt controller model, since interrupt routing is encoded with
CPU bitmap and EIOINTC node combined method
On 2024/8/21 下午4:15, Huacai Chen wrote:
On Tue, Aug 20, 2024 at 12:02 PM maobibo wrote:
Huacai,
On 2024/8/19 下午9:34, Huacai Chen wrote:
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
Interrupts can be routed to maximal four virtual CPUs with one HW
EIOINTC interrupt
On 2024/8/21 下午4:13, Huacai Chen wrote:
On Tue, Aug 20, 2024 at 11:21 AM maobibo wrote:
Huacai,
Thanks for reviewing my patch.
I reply inline.
On 2024/8/19 下午9:32, Huacai Chen wrote:
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
Export kernel paravirt features to user
Huacai,
On 2024/8/19 下午9:34, Huacai Chen wrote:
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
Interrupts can be routed to maximal four virtual CPUs with one HW
EIOINTC interrupt controller model, since interrupt routing is encoded with
CPU bitmap and EIOINTC node combined method
Huacai,
Thanks for reviewing my patch.
I reply inline.
On 2024/8/19 下午9:32, Huacai Chen wrote:
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
Export kernel paravirt features to user space, so that VMM can control
the single paravirt feature. By default paravirt features will be
On 2024/8/11 上午4:46, Thomas Gleixner wrote:
On Mon, Aug 05 2024 at 15:35, Bibo Mao wrote:
Interrupts can be routed to maximal four virtual CPUs with one external
hardware interrupt. Add the extioi virt extension support so that
Interrupts can be routed to 256 vcpus on hypervisor mode.
inte
Hi Chenyu,
On 2024/8/2 下午3:56, Chen Yu wrote:
On 2024-08-02 at 09:27:32 +0800, maobibo wrote:
Hi Chenyu,
On 2024/8/1 下午10:40, Chen Yu wrote:
Hi Bibo,
On 2024-08-01 at 16:00:19 +0800, maobibo wrote:
Chenyu,
I do not know much about x86, just give some comments(probably incorrected)
from
Hi Chenyu,
On 2024/8/1 下午10:40, Chen Yu wrote:
Hi Bibo,
On 2024-08-01 at 16:00:19 +0800, maobibo wrote:
Chenyu,
I do not know much about x86, just give some comments(probably incorrected)
from the code.
On 2024/7/29 下午2:52, Chen Yu wrote:
X86_FEATURE_HYPERVISOR YYY N
Chenyu,
I do not know much about x86, just give some comments(probably
incorrected) from the code.
On 2024/7/29 下午2:52, Chen Yu wrote:
The kernel can change spinlock behavior when running as a guest. But
this guest-friendly behavior causes performance problems on bare metal.
So there's a 'vir
On 2024/7/30 下午4:46, Chen Yu wrote:
Hi Bibo,
On 2024-07-30 at 09:21:45 +0800, maobibo wrote:
Chenyu,
Sorry to bother you, I am porting pv spinlock to LoongArch platform, I do
not know the history about function virt_spin_lock().
When CONFIG_PARAVIRT_SPINLOCKS is enabled, there is
Chenyu,
Sorry to bother you, I am porting pv spinlock to LoongArch platform, I
do not know the history about function virt_spin_lock().
When CONFIG_PARAVIRT_SPINLOCKS is enabled, there is pv_enabled() before
virt_spin_lock(), it seems that virt_spin_lock is never called in this
condition.
7846b618e0a4c3e0099d1d4512722b39ca99]
url:
https://github.com/intel-lab-lkp/linux/commits/Bibo-Mao/LoongArch-KVM-Add-paravirt-qspinlock-in-kvm-side/20240723-160536
base: 7846b618e0a4c3e0099d1d4512722b39ca99
patch link:
https://lore.kernel.org/r/20240723073825.1811600-3-maobibo%40loongson.cn
patch
On 2024/7/8 下午5:47, Huacai Chen wrote:
On Mon, Jul 8, 2024 at 9:16 AM maobibo wrote:
On 2024/7/6 下午5:41, Huacai Chen wrote:
On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
Huacai,
On 2024/7/6 上午11:00, Huacai Chen wrote:
Hi, Bibo,
On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote
On 2024/7/6 下午5:41, Huacai Chen wrote:
On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
Huacai,
On 2024/7/6 上午11:00, Huacai Chen wrote:
Hi, Bibo,
On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
Steal time feature is added here in kvm side, VM can search supported
features provided by
Huacai,
On 2024/7/6 上午11:00, Huacai Chen wrote:
Hi, Bibo,
On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
Steal time feature is added here in kvm side, VM can search supported
features provided by KVM hypervisor, feature KVM_FEATURE_STEAL_TIME
is added here. Like x86, steal time structure is
On 2024/5/8 下午1:00, Huacai Chen wrote:
On Tue, May 7, 2024 at 11:06 AM maobibo wrote:
On 2024/5/7 上午10:05, Huacai Chen wrote:
On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
On 2024/5/6 下午10:17, Huacai Chen wrote:
On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
On 2024/5/6 下午5:40
On 2024/5/7 上午10:05, Huacai Chen wrote:
On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
On 2024/5/6 下午10:17, Huacai Chen wrote:
On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
On 2024/5/6 下午5:40, Huacai Chen wrote:
On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
On 2024/5/6 下午4:59
On 2024/5/6 下午10:17, Huacai Chen wrote:
On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
On 2024/5/6 下午5:40, Huacai Chen wrote:
On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
On 2024/5/6 下午4:59, Huacai Chen wrote:
On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
On 2024/5/6 下午3:06
On 2024/5/6 下午5:40, Huacai Chen wrote:
On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
On 2024/5/6 下午4:59, Huacai Chen wrote:
On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
On 2024/5/6 下午3:06, Huacai Chen wrote:
Hi, Bibo,
On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
On 2024/5
On 2024/5/6 下午4:59, Huacai Chen wrote:
On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
On 2024/5/6 下午3:06, Huacai Chen wrote:
Hi, Bibo,
On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
On 2024/5/6 上午9:49, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote
On 2024/5/6 下午3:06, Huacai Chen wrote:
Hi, Bibo,
On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
On 2024/5/6 上午9:49, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
Physical cpuid is used for interrupt routing for irqchips such as
ipi/msi/extioi interrupt
On 2024/5/6 上午9:53, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
PARAVIRT option and pv ipi is added on guest kernel side, function
pv_ipi_init() is to add ipi sending and ipi receiving hooks. This function
firstly checks whether system runs on VM mode. If k
On 2024/5/6 上午9:49, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
Physical cpuid is used for interrupt routing for irqchips such as
ipi/msi/extioi interrupt controller. And physical cpuid is stored
at CSR register LOONGARCH_CSR_CPUID, it can not be changed on
On 2024/5/6 上午9:45, Huacai Chen wrote:
Hi, Bibo,
I have done an off-list discussion with some KVM experts, and they
think user-space have its right to know PV features, so cpucfg
solution is acceptable.
And I applied this series with some modifications at
https://git.kernel.org/pub/scm/linux
On 2024/5/6 上午9:54, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
On LoongArch system, there is hypercall instruction special for
virtualization. When system executes this instruction on host side,
there is illegal instruction exception reported, however it w
Huacai,
Many thanks for reviewing pv ipi patchset.
And I reply inline.
On 2024/5/6 上午9:49, Huacai Chen wrote:
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
Physical cpuid is used for interrupt routing for irqchips such as
ipi/msi/extioi interrupt controller. And physical cpuid i
On 2024/4/30 下午4:23, Huacai Chen wrote:
Hi, Bibo,
On Tue, Apr 30, 2024 at 9:45 AM Bibo Mao wrote:
Percpu struct kvm_steal_time is added here, its size is 64 bytes and
also defined as 64 bytes, so that the whole structure is in one physical
page.
When vcpu is onlined, function pv_enable_st
On 2024/4/5 下午7:58, Paolo Bonzini wrote:
The .change_pte() MMU notifier callback was intended as an
optimization. The original point of it was that KSM could tell KVM to flip
its secondary PTE to a new location without having to first zap it. At
the time there was also an .invalidate_page() ca
On 2024/4/2 上午10:49, Xi Ruoyao wrote:
On Tue, 2024-04-02 at 09:43 +0800, maobibo wrote:
Sorry for the late reply, but I think it may be a bit non-constructive
to repeatedly submit the same code without due explanation in our
previous review threads. Let me try to recollect some of the
On 2024/4/2 上午10:49, Xi Ruoyao wrote:
On Tue, 2024-04-02 at 09:43 +0800, maobibo wrote:
Sorry for the late reply, but I think it may be a bit non-constructive
to repeatedly submit the same code without due explanation in our
previous review threads. Let me try to recollect some of the
On 2024/3/24 上午3:02, WANG Xuerui wrote:
On 3/15/24 16:07, Bibo Mao wrote:
Instruction cpucfg can be used to get processor features. And there
is trap exception when it is executed in VM mode, and also it is
to provide cpu features to VM. On real hardware cpucfg area 0 - 20
is used. Here one
On 2024/3/24 上午2:40, WANG Xuerui wrote:
On 3/15/24 16:11, Bibo Mao wrote:
[snip]
+KVM hypercall ABI
+=
+
+Hypercall ABI on KVM is simple, only one scratch register a0 and at most
+five generic registers used as input parameter. FP register and
vector register
+is not used for
On 2024/3/6 上午2:26, WANG Xuerui wrote:
On 3/4/24 17:10, maobibo wrote:
On 2024/3/2 下午5:41, WANG Xuerui wrote:
On 3/2/24 16:47, Bibo Mao wrote:
[snip]
+Querying for existence
+==
+
+To find out if we're running on KVM or not, cpucfg can be used with
On 2024/3/2 下午5:41, WANG Xuerui wrote:
On 3/2/24 16:47, Bibo Mao wrote:
Add documentation topic for using pv_virt when running as a guest
on KVM hypervisor.
Signed-off-by: Bibo Mao
---
Documentation/virt/kvm/index.rst | 1 +
.../virt/kvm/loongarch/hypercalls.rst | 7
On 2024/2/27 下午6:19, WANG Xuerui wrote:
On 2/27/24 18:12, maobibo wrote:
On 2024/2/27 下午5:10, WANG Xuerui wrote:
On 2/27/24 11:14, maobibo wrote:
On 2024/2/27 上午4:02, Jiaxun Yang wrote:
在2024年2月26日二月 上午8:04，maobibo写道：
On 2024/2/26 下午2:12, Huacai Chen wrote:
On Mon, Feb 26, 2024 at
On 2024/2/27 下午5:10, WANG Xuerui wrote:
On 2/27/24 11:14, maobibo wrote:
On 2024/2/27 上午4:02, Jiaxun Yang wrote:
在2024年2月26日二月 上午8:04，maobibo写道：
On 2024/2/26 下午2:12, Huacai Chen wrote:
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi
On 2024/2/27 下午5:05, Xi Ruoyao wrote:
On Tue, 2024-02-27 at 15:09 +0800, maobibo wrote:
It is difficult to find an area unused by HW for CSR method since the
small CSR ID range.
We may use IOCSR instead. In kernel/cpu-probe.c there are already some
IOCSR reads.
yes, IOCSR can be used
On 2024/2/27 下午1:23, Jiaxun Yang wrote:
在2024年2月27日二月 上午3:14，maobibo写道：
On 2024/2/27 上午4:02, Jiaxun Yang wrote:
在2024年2月26日二月 上午8:04，maobibo写道：
On 2024/2/26 下午2:12, Huacai Chen wrote:
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi
On 2024/2/27 上午4:02, Jiaxun Yang wrote:
在2024年2月26日二月 上午8:04，maobibo写道：
On 2024/2/26 下午2:12, Huacai Chen wrote:
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Instruction cpucfg
On 2024/2/26 下午2:12, Huacai Chen wrote:
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Instruction cpucfg can be used to get processor features. And there
is trap exception when it is
On 2024/2/26 下午1:25, WANG Xuerui wrote:
Hi,
On 2/26/24 10:04, maobibo wrote:
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Instruction cpucfg can be used to get processor features. And there
is trap exception when it is executed in
On 2024/2/24 下午5:19, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi sending, and two iocsr access on ipi receiving
which is ipi interrupt handler. On VM mode all iocsr
On 2024/2/24 下午5:15, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Paravirt interface pv_ipi_init() is added here for guest kernel, it
firstly checks whether system runs on VM mode. If kernel runs on VM mode,
it will call function kvm_para_available() to det
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Instruction cpucfg can be used to get processor features. And there
is trap exception when it is executed in VM mode, and also it is
to provide cpu features to VM. On real hardware cpucfg are
On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
Instruction cpucfg can be used to get processor features. And there
is trap exception when it is executed in VM mode, and also it is
to provide cpu features to VM. On real hardware cpucfg are
On 2024/2/22 下午5:34, WANG Xuerui wrote:
On 2/17/24 11:15, maobibo wrote:
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks
for providing microbenchmark numbers! But it seems the more
comprehensive
On 2024/2/19 下午5:02, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 3:37 PM maobibo wrote:
On 2024/2/19 下午3:16, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
On 2024/2/19 上午10:45, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
On
On 2024/2/19 下午5:38, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 5:21 PM maobibo wrote:
On 2024/2/19 下午4:48, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
On 2024/2/19 上午10:42, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
The
On 2024/2/19 下午4:48, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
On 2024/2/19 上午10:42, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
The patch adds paravirt interface for guest kernel, function
pv_guest_initi() firstly checks
On 2024/2/19 下午3:16, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
On 2024/2/19 上午10:45, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi
On 2024/2/19 上午10:45, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi sending, and two iocsr access on ipi receiving
which is ipi interrupt handler. On VM mode all iocsr
On 2024/2/19 上午10:42, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
The patch adds paravirt interface for guest kernel, function
pv_guest_initi() firstly checks whether system runs on VM mode. If kernel
runs on VM mode, it will call function kvm_para_availabl
On 2024/2/19 上午10:41, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
Huacai,
Thanks for your reviewing, I reply inline.
On 2024/2/19 上午10:39, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
This patch refines ipi handling on LoongArch platform, there are
three changes with this patch.
1. Add generic get_percpu_irq() api, replace
On 2024/2/15 下午6:25, WANG Xuerui wrote:
On 2/15/24 18:11, WANG Xuerui wrote:
Sorry for the late reply (and Happy Chinese New Year), and thanks for
providing microbenchmark numbers! But it seems the more comprehensive
CoreMark results were omitted (that's also absent in v3)? While the
Of c
On 2024/1/29 下午9:11, Huacai Chen wrote:
Hi, Bibo,
Without this patch I can also create a SMP VM, so what problem does
this patch want to solve?
With ipi irqchip, physical cpuid is used for dest cpu rather than
logical cpuid. And if ipi device is emulated in qemu side, there is
find_cpu_by_a
On 2024/1/29 下午9:10, Huacai Chen wrote:
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi sender and two iocsr access on ipi receiver
which is ipi interrupt handler. On VM mode all iocsr reg
On 2024/1/29 下午8:38, Huacai Chen wrote:
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
This patch refines ipi handling on LoongArch platform, there are
three changes with this patch.
1. Add generic get_percpu_irq api, replace some percpu irq function
such as get_ipi_irq/get_pmc_
On 2024/1/3 下午4:14, Juergen Gross wrote:
On 03.01.24 09:00, maobibo wrote:
On 2024/1/3 下午3:40, Jürgen Groß wrote:
On 03.01.24 08:16, Bibo Mao wrote:
The patch add paravirt interface for guest kernel, it checks whether
system runs on VM mode. If it is, it will detect hypervisor type. And
On 2024/1/3 下午3:40, Jürgen Groß wrote:
On 03.01.24 08:16, Bibo Mao wrote:
The patch add paravirt interface for guest kernel, it checks whether
system runs on VM mode. If it is, it will detect hypervisor type. And
returns true it is KVM hypervisor, else return false. Currently only
KVM hypervi
On 06/30/2020 06:42 PM, maobibo wrote:
>
>
> On 06/30/2020 06:09 PM, Kirill A. Shutemov wrote:
>> On Wed, Jun 24, 2020 at 05:26:30PM +0800, Bibo Mao wrote:
>>> update_mmu_cache_pmd is used to update tlb for the pmd entry by
>>> software. On MIPS system, th
On 06/30/2020 06:09 PM, Kirill A. Shutemov wrote:
> On Wed, Jun 24, 2020 at 05:26:30PM +0800, Bibo Mao wrote:
>> update_mmu_cache_pmd is used to update tlb for the pmd entry by
>> software. On MIPS system, the tlb entry indexed by page fault
>> address maybe exists already, only that tlb entry m
On 06/25/2020 08:30 AM, Mike Kravetz wrote:
> On 6/24/20 2:26 AM, Bibo Mao wrote:
>> When set_pmd_at is called in function do_huge_pmd_anonymous_page,
>> new tlb entry can be added by software on MIPS platform.
>>
>> Here add update_mmu_cache_pmd when pmd entry is set, and
>> update_mmu_cache_pm
On 06/22/2020 11:48 PM, Thomas Bogendoerfer wrote:
> On Sat, Jun 20, 2020 at 11:47:35AM +0800, maobibo wrote:
>>
>>
>> On 06/17/2020 07:14 PM, Thomas Bogendoerfer wrote:
>>> On Tue, Jun 16, 2020 at 06:34:21PM +0800, maobibo wrote:
>>>>
>>>>
On 06/23/2020 10:26 AM, Nathan Chancellor wrote:
> On Tue, Jun 16, 2020 at 01:45:27PM -0700, Nitin Gupta wrote:
>> For some applications, we need to allocate almost all memory as
>> hugepages. However, on a running system, higher-order allocations can
>> fail if the memory is fragmented. Linux k
On 06/17/2020 07:14 PM, Thomas Bogendoerfer wrote:
> On Tue, Jun 16, 2020 at 06:34:21PM +0800, maobibo wrote:
>>
>>
>> On 06/15/2020 06:14 PM, Thomas Bogendoerfer wrote:
>>> On Wed, Jun 03, 2020 at 05:42:13PM +0800, Bibo Mao wrote:
>>>> Function set_pmd
On 06/15/2020 06:14 PM, Thomas Bogendoerfer wrote:
> On Wed, Jun 03, 2020 at 05:42:13PM +0800, Bibo Mao wrote:
>> Function set_pmd_at is to set pmd entry, if tlb entry need to
>> be flushed, there exists pmdp_huge_clear_flush alike function
>> before set_pmd_at is called. So it is not necessary
On 06/05/2020 05:39 PM, Jiaxun Yang wrote:
> On Fri, 5 Jun 2020 17:11:05 +0800
> Bibo Mao wrote:
>
>> On MIPS system which has rixi hardware bit, page access bit is not
>> set in pgrot. For memory reading, there will be one page fault to
>> allocate physical page; however valid bit is not set
On 06/04/2020 05:00 AM, Linus Torvalds wrote:
> On Tue, Jun 2, 2020 at 5:55 AM Thomas Bogendoerfer
> wrote:
>>
>> Bibo Mao (4):
>> mm/memory.c: Add memory read privilege on page fault handling
>
> Hmm. That's a horribly named commit, but can you clarify why this
> didn't just use the exi
On 05/29/2020 03:23 AM, Andrew Morton wrote:
> On Wed, 27 May 2020 10:25:18 +0800 Bibo Mao wrote:
>
>> If two threads concurrently fault at the same page, the thread that
>> won the race updates the PTE and its local TLB. For now, the other
>> thread gives up, simply does nothing, and continue
On 05/28/2020 04:55 AM, Hugh Dickins wrote:
> On Tue, 19 May 2020, maobibo wrote:
>> On 05/19/2020 04:57 AM, Andrew Morton wrote:
>>> On Mon, 18 May 2020 13:08:49 +0800 Bibo Mao wrote:
>>>
>>>> On mips platform, hw PTE entry valid bit is set in pte_m
On 05/25/2020 04:31 PM, Sergei Shtylyov wrote:
> On 25.05.2020 11:12, Sergei Shtylyov wrote:
>
>>> It is not necessary to flush tlb page on all CPUs if suitable PTE
>>> entry exists already during page fault handling, just updating
>>> TLB is fine.
>>>
>>> Here redefine flush_tlb_fix_spurious_f
On 05/26/2020 05:42 AM, Andrew Morton wrote:
> On Mon, 25 May 2020 10:52:37 +0800 Bibo Mao wrote:
>
>> It is not necessary to flush tlb page on all CPUs if suitable PTE
>> entry exists already during page fault handling, just updating
>> TLB is fine.
>>
>> Here redefine flush_tlb_fix_spurious_
On 05/26/2020 05:44 AM, Andrew Morton wrote:
> On Mon, 25 May 2020 10:52:39 +0800 Bibo Mao wrote:
>
>> Here add pte_sw_mkyoung function to make page readable on MIPS
>> platform during page fault handling. This patch improves page
>> fault latency about 10% on my MIPS machine with lmbench
>> l
On 05/22/2020 03:22 AM, Andrew Morton wrote:
> On Thu, 21 May 2020 11:30:35 +0800 Bibo Mao wrote:
>
>> If two threads concurrently fault at the same address, the thread that
>> won the race updates the PTE and its local TLB. For now, the other
>> thread gives up, simply does nothing, and conti
On 05/20/2020 09:30 AM, Andrew Morton wrote:
> On Tue, 19 May 2020 18:03:29 +0800 Bibo Mao wrote:
>
>> Here add pte_sw_mkyoung function to make page readable on MIPS
>> platform during page fault handling. This patch improves page
>> fault latency about 10% on my MIPS machine with lmbench
>> l
On 05/20/2020 09:26 AM, Andrew Morton wrote:
> On Tue, 19 May 2020 18:03:28 +0800 Bibo Mao wrote:
>
>> If two threads concurrently fault at the same address, the thread that
>> won the race updates the PTE and its local TLB. For now, the other
>> thread gives up, simply does nothing, and conti
On 05/19/2020 04:57 AM, Andrew Morton wrote:
> On Mon, 18 May 2020 13:08:49 +0800 Bibo Mao wrote:
>
>> On mips platform, hw PTE entry valid bit is set in pte_mkyoung
>> function, it is used to set physical page with readable privilege.
>
> pte_mkyoung() seems to be a strange place to set the
On 05/16/2020 05:34 PM, maobibo wrote:
>
>
> On 05/15/2020 09:50 PM, David Hildenbrand wrote:
>> On 14.05.20 08:50, Bibo Mao wrote:
>>> If there are two threads hitting page fault at the address, one
>>> thread updates pte entry and local tlb, the other thr
On 05/16/2020 04:40 AM, Andrew Morton wrote:
> On Fri, 15 May 2020 12:10:08 +0800 Bibo Mao wrote:
>
>> If there are two threads hitting page fault at the same page,
>> one thread updates PTE entry and local TLB, the other can
>> update local tlb also, rather than give up and do page fault
>> a
On 05/15/2020 09:50 PM, David Hildenbrand wrote:
> On 14.05.20 08:50, Bibo Mao wrote:
>> If there are two threads hitting page fault at the address, one
>> thread updates pte entry and local tlb, the other thread can update
>> local tlb also, rather than give up and let page fault happening
>> a
On 05/14/2020 05:37 PM, Sergei Shtylyov wrote:
> On 14.05.2020 12:35, Sergei Shtylyov wrote:
>
>>> From: bibo mao
>>>
>>> If there are two threads reading the same memory and tlb miss happens,
>>> one thread fills pte entry, the other reads new pte value during page fault
>>> handling. PTE val
On 05/14/2020 05:33 PM, Mike Rapoport wrote:
> On Thu, May 14, 2020 at 10:17:57AM +0800, Bibo Mao wrote:
>> From: bibo mao
>>
>> If there are two threads reading the same memory and tlb miss happens,
>> one thread fills pte entry, the other reads new pte value during page fault
>> handling. PTE
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