From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY in a CP11x DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/ar
From: Konstantin Porotchkin
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 21 ++--
From: Konstantin Porotchkin
The new file name is marvell,armada-3700-utmi-phy.yaml
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml | 57
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI PHY
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml | 109
1 file changed, 109 insertions(+)
create mode 100644
Documentation/devicetree/
From: Konstantin Porotchkin
This series of patches adds a new PHY driver for supporting CP110 UTMI
PHY in Linux. Currently the functionality of USB ports connected to
this PHY depends on boot loader setup.
The new driver eliminates kernel configuration dependency from the boot
loader.
v3:
- reb
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY driver allowing the USB2
port configuration independently from the boot loader setup.
The CP110/CP115 dies have 2 UTMI PHYs that could be connected
to two USB host controllers or to single USB device controller.
Since there is onl
From: Konstantin Porotchkin
The function name is used for selecting MPP functionality and
should be unique within function names of the same pin.
This patch fixes function names for MPP54 and MPP55 that
have two different functions named the same.
Signed-off-by: Konstantin Porotchkin
---
drive
From: Konstantin Porotchkin
These patches are fixing the CP110 pin control driver and the related
documentation.
Current CP110 pin control driver uses two different MPP functions named
the same (sdio) in MPP54 and MPP55 definitions.
Since these names are used for the MPP functionality selection,
From: Konstantin Porotchkin
Fix the pin function names for MPP54 and MPP55.
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt | 4
++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bind
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI driver
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 78
++--
1 file changed, 72 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindin
From: Konstantin Porotchkin
Enable support for CP110 UTMI driver in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 21 +
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI driver in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
From: Konstantin Porotchkin
This series of patches adds a new PHY driver for supporting CP110 UTMI
PHY in Linux. Currently the functionality of USB ports connected to
this PHY depends on boot loader setup.
The new driver eliminates kernel configuration dependency from the boot
loader.
v2:
- ext
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY driver allowing the USB2
port configuration independently from the boot loader setup.
The CP110/CP115 dies have 2 UTMI PHYs that could be connected
to two USB host controllers or to single USB device controller.
Since there is onl
From: Grzegorz Jaszczyk
This patch introduces support for cpu clk driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
cpu clk registers, which are part of dfx register set, will not be
possible from non-secure world.
The ARM Trusted Firmware exposes SiP
From: Grzegorz Jaszczyk
This patch introduces support for ap806 thermal driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
thermal registers, which are part of dfx register set, will not be
possible from non-secure world. Due to above the ARM Trusted Fi
From: Konstantin Porotchkin
These patches enable usage of Arm Trusted Firmware SIP services on
Marvell Armada plaforms for accessing system registers that are not
normally accessible from kernel or user space (EL1/EL0), like DFX
registers group.
v2:
* use separate legacy/smc regmap functions reg
From: Grzegorz Jaszczyk
This patch introduces support for cpu clk driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
cpu clk registers, which are part of dfx register set, will not be
possible from non-secure world.
The ARM Trusted Firmware exposes SiP
From: Grzegorz Jaszczyk
This patch introduces support for ap806 thermal driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
thermal registers, which are part of dfx register set, will not be
possible from non-secure world. Due to above the ARM Trusted Fi
From: Konstantin Porotchkin
These patches enable usage of Arm Trusted Firmware SIP services on
Marvell Armada plaforms for accessing system registers that are not
normally accessible from kernel or user space (EL1/EL0), like DFX
registers group.
v2:
* use separate legacy/smc regmap functions reg
From: Konstantin Porotchkin
The AP SDHCI on Armada 8040 DB board utilizes 8-bit data lines.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
From: Ben Peled
Add on-board i2c EEPROMs U37 and U38
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm6
From: Ben Peled
Add on-board i2c EEPROMs U41 and U51
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64
From: Stefan Chulski
Enable dma coherence for PCIe and memory-mapped devices
on A3700 platform
Signed-off-by: Stefan Chulski
Signed-off-by: Marcin Wojtas
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Grzegorz Jaszczyk
On Armada 3720 board there is serial emprom M24C64 at address 0x57,
reflect it in device-tree.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
1 file changed, 6 insertions(+)
diff --g
From: Grzegorz Jaszczyk
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts
From: Grzegorz Jaszczyk
Adding phy description to pcie, sata and usb will allow appropriate drivers
to configure marvell comphy-a3700 accordingly.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
1 file chang
From: Konstantin Porotchkin
All A7K/A8K boards are using NAND chip that supports
8 bit ECC strength. Using lower ECC strength is not recommended
by the flash manufacturer and may cause data corruption.
This patch changes the nand-ecc-strength value from 4 to 8.
Signed-off-by: Konstantin Porotchk
From: Konstantin Porotchkin
Add SDIO mode pin control configuration for CP0 in Armada
70x0 and 80x0 SoCs.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++
2 files changed, 12 insertions(+)
From: Konstantin Porotchkin
Add GPIO regulator for controlling CP0 eMMC voltage (3.3V/1.8V)
Update CP0 SDHCI parameters in A7K/A8K boards DTS files.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 17 -
arch/arm64/boot/dts/marvell/armad
From: Konstantin Porotchkin
Select the AP SDHCI PHY slow mode for AP806 die only (move it
from armada-ap80x.dtsi to armada-ap806.dtsi). This will allow
running AP807 based devices at HS400 speed.
Remove Ap SDHCI slow mode property from MacchiatoBin board DTS
since it is already selected on the So
From: Konstantin Porotchkin
This set of patches include various device tree additions and fixes
for Marvell Armada SoC families A3700/A7K/A8K.
These changes are ported from Marvell SDK release files.
v2:
- Rebase on top of Linus master branch 5.11-rc7
- Move AP SDHCI "slow-mode" property from AP
From: Konstantin Porotchkin
Replace wrong regulator in AP0 eMMC definition on MacchiatoBIN
board with 3.3V regulator.
The MacchiatoBIN board has no 1.8V regulator connected to AP0
eMMC (ap0_sdhci0) interface.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-mcbi
From: Konstantin Porotchkin
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
*
From: Konstantin Porotchkin
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS f
From: Stefan Chulski
This patch enables eth0 10G interface on CN9130-DB paltforms and
eth0 10G and eth3 10G interfaces on CN9131-DB.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
arch/arm64/boot/dts/marvell/cn9131-db.
From: Konstantin Porotchkin
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/
From: Konstantin Porotchkin
This patch series contains the following changes/fixes:
1. Add support for Armada CN913x Development Board topology "B"
2. Add support for Armada CN913x Reference Design boards (CRB)
3. Fixes the CP11X references in PHY binding document
4. Fixes the NAND paritioninig s
From: Grzegorz Jaszczyk
The cp11x references in dts has changed, reflect it in comphy
documentation.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++--
1 file changed, 6 insertions(+), 6 delet
From: Konstantin Porotchkin
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS f
From: Konstantin Porotchkin
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
*
From: Stefan Chulski
This patch enables eth0 10G interface on CN9130-DB paltforms.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/
From: Grzegorz Jaszczyk
The cp11x references in dts has changed, reflect it in comphy
documentation.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++--
1 file changed, 6 insertions(+), 6 delet
From: Konstantin Porotchkin
This patch series contains the following changes/fixes:
1. Add support for Armada CN913x Development Board topology "B"
2. Add support for Armada CN913x Reference Design boards (CRB)
3. Fixes the CP11X references in PHY binding document
4. Fixes the NAND paritioninig s
From: Konstantin Porotchkin
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/
From: Konstantin Porotchkin
Update the settings for AP806 SDHCI interface according to
latest Xenon drivers changes.
- no need to select the PHY slow mode anymore
- recommended to add HS400 support at 1.8V signalling on AP806-B0
- fix the bus witdth for A8040 DB from 4 to 8 bits.
Signed-off-by:
From: Grzegorz Jaszczyk
Adding phy description to pcie, sata and usb will allow appropriate drivers
to configure marvell comphy-a3700 accordingly.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
1 file chang
From: Konstantin Porotchkin
This set of patches include various device tree additions and fixes
for Marvell Armada SoC families A3700/A7K/A8K.
These changes are ported from Marvell SDK release files.
Ben Peled (2):
dts: marvell: add 2 eeprom properties to A8K DB device tree
dts: marvell: add
From: Konstantin Porotchkin
Add GPIO regulator for controlling CP0 eMMC voltage (3.3V/1.8V)
Update CP0 SDHCI parameters in A7K/A8K boards DTS files.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 17 -
arch/arm64/boot/dts/marvell/armad
From: Grzegorz Jaszczyk
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts
From: Ben Peled
Add on-board i2c EEPROMs U37 and U38
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm6
From: Konstantin Porotchkin
All A7K/A8K boards are using NAND chip that supports
8 bit ECC strength. Using lower ECC strength is not recommended
by the flash manufacturer and may cause data corruption.
This patch changes the nand-ecc-strength value from 4 to 8.
Signed-off-by: Konstantin Porotchk
From: Grzegorz Jaszczyk
On Armada 3720 board there is serial emprom M24C64 at address 0x57,
reflect it in device-tree.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
1 file changed, 6 insertions(+)
diff --g
From: Stefan Chulski
Enavble PCIe dma coherence for A3700 platform
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64
From: Ben Peled
Add on-board i2c EEPROMs U41 and U51
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64
From: Konstantin Porotchkin
Replace wrong regulator in AP0 eMMC definition on MacchiatoBIN
board with 3.3V regulator.
The MacchiatoBIN board has no 1.8V regulator connected to AP0
eMMC (ap0_sdhci0) interface.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-mcbi
From: Konstantin Porotchkin
Add SDIO mode pin control configration for CP0 on A8K DB.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI driver
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 69
++--
1 file changed, 63 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindin
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI driver in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY driver allowing the USB2
port configuration independently from the boot loader setup.
The CP110/CP115 dies have 2 UTMI PHYs that could be connected
to two USB host controllers or to single USB device controller.
Since there is onl
From: Konstantin Porotchkin
Enable support for CP110 UTMI driver in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 12
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 --
From: Konstantin Porotchkin
This series of patches adds a new PHY driver for supporting CP110 UTMI
PHY in Linux. Currently the functionality of USB ports connected to
this PHY depends on boot loader setup.
The new driver eliminates kernel configuration dependency from the boot
loader.
Konstanti
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