[RESEND PATCH] usb: dwc2: Add reset control to dwc2

From: Dinh Nguyen Allow for platforms that have a reset controller driver in place to bring the USB IP out of reset. Signed-off-by: Dinh Nguyen Acked-by: John Youn Tested-by: Stefan Wahren Acked-by: Felipe Balbi --- v7: Use devm_reset_control_get_optional() v6: fix 80 line checkpatch warning

[PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill()

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill()

[PATCH] Doc: Micrel-ksz90x1.txt: Update the Micrel phy documentation for ksz9031

From: Dinh Nguyen Update the Micrel phy documentation for the KSZ9031 PHY to represent how the actual values are calculated from the code. Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/net/micrel-ksz90x1.txt | 73 ++ 1 file changed, 73 insertions(+) diff --git

[PATCH] arm: socfpga_defconfig: enable USB dual-role and cleanup

From: Dinh Nguyen Enable USB OTG dual-role and a bit of clean up by using make savedefconfig. Signed-off-by: Dinh Nguyen --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfp

[PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. The SDRAM ECC is a separate Kconfig option because: 1) the SDRAM preparation

[PATCH] EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN

From: Dinh Nguyen The bootloader may or may not enable the ECC_CORR_EN bit. By not enabling ECC_CORR_EN, when error happens, it is the user's responsibility to perform a full SDRAM scrub. Remove the check for ECC_CORR_EN. Signed-off-by: Dinh Nguyen --- drivers/edac/altera_edac.h | 3 +-- 1 fi

[PATCHv4] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v4: Add a non-zero ranges property for /soc node v3: change #address-cells and #size-cells to <2> change the GIC address to 0xfffc1000 update the GIC virtual CPU reg length to 0x2

[PATCv3] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v3: change #address-cells and #size-cells to <2> change the GIC address to 0xfffc1000 update the GIC virtual CPU reg length to 0x2000 v2: use interrupt-affinity for pmu node ---

[PATCHv2] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- v2: use interrupt-affinity for pmu node --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/al

[PATCH] arm64: dts: Add base stratix 10 dtsi

From: Dinh Nguyen Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen --- arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/altera/Makefile| 5 + arch/a

[PATCHv2 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager that is used for bringing peri

[PATCHv2 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen v2: For the reset driver, assume a modrst-offset of 0x10 in order to support legacy boards that do have the property.. v1: This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5

[PATCHv2 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++ 1 file changed, 110 insertion

[PATCHv2 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

From: Dinh Nguyen The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++ arch/arm/boot

[PATCHv2 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 22

[PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

From: Dinh Nguyen In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the device tree entry. The 'altr,modrst-offset' property is the first register into the reset manager that is used for bringing peri

[PATCH 2/4] ARM: socfpga: dts: add "altr,modrst-offset" property

From: Dinh Nguyen The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 2 ++ arch/arm/boot

[PATCH 4/4] ARM: socfpga: dts: Add resets for EMACs on Arria10

From: Dinh Nguyen Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 22

[PATCH 0/4] reset: socfpga: Add reset driver support for Arria10 platform

From: Dinh Nguyen Hi, This patch series adds reset driver support for the SoCFPGA Arria10 SOC. The reset manager on the Arria10 is very similar to the one on Cyclone5/Arria5, thus I think it's best to try to re-use the same reset driver. The biggest difference between the reset manager on Arria

[PATCH 1/4] dt-bindings: Add reset manager offsets for Arria10

From: Dinh Nguyen The reset manager for is pretty similar to the one for SoCFPGA cyclone5/arria5 except for a few offsets. This patch adds those offsets. Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 +++ 1 file changed, 110 insertion

[PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen --- v2: remove

[PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen --- arch/arm/b

[PATCH] ARM: socfpga: add reset for the Arria 10 platform

From: Dinh Nguyen Since the Arria10's reset register offset is different from the Cyclone/Arria 5, it's best to add a new DT_MACHINE_START() for the Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/core.h| 1 + arch/arm/mach-socfpga/socfpga.c | 26 ++

[PATCHv2 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Tero Kristo --- drivers/clk/ti/apll.c |4 +--- drivers/clk/ti/composite.c |4 +--- drivers/clk/ti/dpll.c |4 +--- drivers/clk/ti/fapll.c |3 +-- driv

[PATCHv2 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Hello, This is v2 of the patchset that makes use of of_clk_parent_fill helper function on various platforms. Thanks, Dinh Nguyen (6): clk: at91: make use of of_clk_parent_fill helper function clk: qoriq: make use of of_clk_parent_fill helper function clk: keystone: make

[PATCHv2 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Boris Brezillon --- drivers/clk/at91/clk-main.c |7 +-- drivers/clk/at91/clk-master.c |7 +-- drivers/clk/at91/clk-programmable.c |7 +-- dri

[PATCHv2 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Tested-by Gabriel Fernandez Cc: Peter Griffin --- drivers/clk/st/clk-flexgen.c |6 ++ drivers/clk/st/clkgen-mux.c |7 ++- 2 files changed, 4 insertions(+), 9 deletio

[PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Maxime Ripard Cc: "Emilio López" --- v2: Add if (of_clk_parent_fill(node, parents, 2) != 2) to clk-a20-gmac.c --- drivers/clk/sunxi/clk-a20-gmac.c|4 +--- drivers/clk/sun

[PATCHv2 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Acked-by: Santosh Shilimkar --- drivers/clk/keystone/pll.c |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/p

[PATCHv2 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen --- drivers/clk/clk-qoriq.c |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index cda90a9..d3f4570 100644

[PATCH 3/6] clk: keystone: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Santosh Shilimkar --- drivers/clk/keystone/pll.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c inde

[PATCH 4/6] clk: st: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Peter Griffin Cc: Gabriel FERNANDEZ --- drivers/clk/st/clk-flexgen.c | 6 ++ drivers/clk/st/clkgen-mux.c | 7 ++- 2 files changed, 4 insertions(+), 9 deletions(-) diff

[PATCH 6/6] clk: ti: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Tero Kristo --- drivers/clk/ti/apll.c | 4 +--- drivers/clk/ti/composite.c | 4 +--- drivers/clk/ti/dpll.c | 4 +--- drivers/clk/ti/fapll.c | 3 +-- drivers/clk/ti/m

[PATCH 1/6] clk: at91: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Boris Brezillon --- drivers/clk/at91/clk-main.c | 7 +-- drivers/clk/at91/clk-master.c | 7 +-- drivers/clk/at91/clk-programmable.c | 7 +-- drivers/c

[PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen Cc: Maxime Ripard Cc: "Emilio López" --- drivers/clk/sunxi/clk-a20-gmac.c| 3 +-- drivers/clk/sunxi/clk-factors.c | 4 +--- drivers/clk/sunxi/clk-sun6i-ar100.c | 3 +-- dr

[PATCH 2/6] clk: qoriq: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen --- drivers/clk/clk-qoriq.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index cda90a9..d3f4570 100644 ---

[PATCH 0/6] clk: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Hello, This patch series makes use of the new of_clk_parent_fill() helper function. This patch series is not intended for v4.2, as I think it's a bit late, but I just wanted to make sure people have time to test it. The series is based on git://git.kernel.org/pub/scm/linux/kern

[PATCHv3 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return t

[PATCHv3 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- v3: none v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/

[PATCHv3 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); Th

[PATCH] EDAC, altera: wrap edac pm with a CONFIG_PM

From: Alan Tull Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen Acked-by: Borislav Petkov --- Hi Boris, Please apply this patch to your for-ne

[RFC/PATCHv2 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- v2: none --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/socfpga/c

[RFC/PATCHv2 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since the following code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); Th

[RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return t

[RFC/PATCHv1 1/2] clk: of: helper for filling parent clock array and return num of parents

From: Dinh Nguyen Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return t

[RFC/PATCHv1 2/2] clk: socfpga: make use of of_clk_parent_fill helper function

From: Dinh Nguyen Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 6 +- drivers/clk/socfpga/clk-pll.c | 7 +-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate.c b/d

[RFC/PATCHv1 0/2] clk: of: add helper function to fill parent clock array

From: Dinh Nguyen Hi, As suggested by Stephen Boyd, this patch adds a helper function that will fill the parent clock array. Since this kind of code is sprinkled all over the platform clock drivers: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The

[PATCH] usb: dwc2: fix unnecessary USB overcurrent condition

From: Dinh Nguyen For platforms that use a ULPI phy, we should enable the external VbusValid signal instead. Signed-off-by: Dinh Nguyen Cc: Gregory Herrero Cc: Mian Yousaf Kaukab Cc: Felipe Balbi --- drivers/usb/dwc2/core.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/us

[PATCH 1/3] ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5

From: Dinh Nguyen Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/platsmp.c | 2 ++ arch/arm/mach-socfpga/socfpga.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/platsmp.c

[PATCH 2/3] ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

From: Dinh Nguyen Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. -

[PATCH 3/3] ARM: socfpga: dts: add enable-method property for cpu nodes

From: Dinh Nguyen Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi

[PATCH 0/3] ARM: socfpga: enable SMP for Arria10

From: Dinh Nguyen Hi, The goal of these 3 patches is to enable SMP on the Arria10 platform. During the process, I found it would be much cleaner to convert the Cyclone5/Arria5 platform to use CPU_METHOD_OF_DECLARE instead of the machine descriptor. The procedure to enable SMP on the Arria10 pla

[PATCHv4 1/2] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 drivers/clk/socfpga/clk.h | 6 +- 2

[PATCHv4 0/2] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing driver with platform lookups. v4

[PATCHv4 2/2] clk: socfpga: add a clock driver for the Arria 10 platform

From: Dinh Nguyen The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen --- v4: Move lookup of syscon for clk_phase to gate_clk_init() Remove unused includes v3: Assign pointer to NULL in

[PATCHv3 1/4] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 drivers/clk/socfpga/clk.h | 6 +- 2

[PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

From: Dinh Nguyen The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen --- v3: Assign pointer to NULL instead of integer 0 per sparse check --- drivers/clk/socfpga/Makefile | 1 +

[PATCHv3 4/4] Documentation: DT bindings: document the clocks for Arria10

From: Dinh Nguyen Update the bindings document for the clocks on the SoCFPGA Arria10 platform. Also fix up a spelling error for the "altr,socfpga-perip-clk". Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/clock/altr_socfpga.txt | 17 +++-- 1 file changed, 11 insert

[PATCHv3 0/4] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing driver with platform lookups. v3

[PATCHv3 3/4] ARM: socfpga: dts: add clocks to the Arria10 platform

From: Dinh Nguyen Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen --- v2: Add the l4_sys_free_clk node --- arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -

[PATCH] dmaengine: pl300: enable the clock to PL330 dma

From: Dinh Nguyen Turn on the clock to the PL330 DMA if there is a clock node provided. Signed-off-by: Dinh Nguyen --- drivers/dma/pl330.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 0e1f567..82eb641 100644 --- a/drivers/dma/pl330.c +

[PATCHv2 4/4] Documentation: DT bindings: document the clocks for Arria10

From: Dinh Nguyen Update the bindings document for the clocks on the SoCFPGA Arria10 platform. Also fix up a spelling error for the "altr,socfpga-perip-clk". Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/clock/altr_socfpga.txt | 17 +++-- 1 file changed, 11 insert

[PATCHv2 1/4] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 drivers/clk/socfpga/clk.h | 6 +- 2

[PATCHv2 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

From: Dinh Nguyen The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/Makefile | 1 + drivers/clk/socfpga/clk-gate-a10.c | 187 +

[PATCHv2 3/4] ARM: socfpga: dts: add clocks to the Arria10 platform

From: Dinh Nguyen Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen --- v2: Add the l4_sys_free_clk node --- arch/arm/boot/dts/socfpga_arria10.dtsi | 309 -

[PATCHv2 0/4] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing driver with platform lookups. v2

[PATCH] MAINTAINERS: socfpga: update the git repo for SoCFPGA

: http://www.rocketboards.org -T: git://git.rocketboards.org/linux-socfpga.git -T: git://git.rocketboards.org/linux-socfpga-next.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT M: Dinh Nguyen -- 2.2.1 -- To

[PATCHv2 2/4] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

From: Dinh Nguyen Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/socf

[PATCHv2 4/4] ARM: socfpga: rename socdk board file to socdk_sdmmc

From: Dinh Nguyen Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10

[PATCHv2 1/4] ARM: socfpga: add cpu1-start-addr for Arria 10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8a05c47..69d616a 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi

[PATCHv2 3/4] ARM: socfpga: dts: enable UART1 for the debug uart

From: Dinh Nguyen Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen --- v2: Add removal of unused aliases --- arch/arm/boot/dts/socfpga_arria10.dtsi | 12 arch/arm/boot/dts/socfpga_arria10_socdk.dts | 8 2 files

[PATCHv2 0/4] Add support for Arria10 devkit

From: Dinh Nguyen Hi, This patchset enables and tidy up support for the Arria10 devkit. Along with this patchset and the patchset for enabling clocks on the Arria10, the devkit can boot Linux. V2: - Patch "ARM: socfpga: dts: enable UART1 for the debug uart" adds the removal of unused aliases

[PATCH RESEND 1/2] ARM: socfpga: Add support for UART1 debug uart for earlyprintk

From: Dinh Nguyen Add support for hardware uart1 for earlyprintk support on Arria10 devkit. Signed-off-by: Dinh Nguyen CC: Russell King --- arch/arm/Kconfig.debug | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/K

[PATCH RESEND 2/2] ARM: socfpga: remove the need to map uart_io_desc

From: Dinh Nguyen All the necessary debug uart mapping is already being done in debug_ll_io_init, there's no need for it here. Signed-off-by: Dinh Nguyen Cc: Russell King --- arch/arm/mach-socfpga/socfpga.c | 9 - 1 file changed, 9 deletions(-) diff --git a/arch/arm/mach-socfpga/socf

[PATCH RESEND] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

From: Dinh Nguyen Document "altr,socfpga-cyclone5", "altr,socfpga-arria5", and "altr,socfpga-arria10". Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.txt | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm

[PATCH 3/7] ARM: socfpga: dts: enable UART1 for the debug uart

From: Dinh Nguyen Arria10 devkit is using UART1 for the debug uart port. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria

[PATCH 0/3] clk: socfpga: Add clock driver for Arria10

From: Dinh Nguyen Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing driver with platform lookups. Di

[PATCH 0/7] ARM: socfpga: Add support for Arria10 devkit

From: Dinh Nguyen Hi, This patchset enables and tidy up support for the Arria10 devkit. Along with this patchset and the patch for enabling clocks on the Arria10, the devkit can boot Linux. Dinh Nguyen (7): ARM: socfpga: add cpu1-start-addr for Arria 10 ARM: socfpga: disable the sdmmc, and

[PATCH 7/7] Documentation: DT bindings: add doc for Altera's SoCFPGA platform

From: Dinh Nguyen Document "altr,socfpga-cyclone5", "altr,socfpga-arria5", and "altr,socfpga-arria10". Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.txt | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm

[PATCH 2/3] clk: socfpga: add a clock driver for the Arria 10 platform

From: Dinh Nguyen The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/Makefile | 1 + drivers/clk/socfpga/clk-gate-a10.c | 187 +

[PATCH 4/7] ARM: socfpga: rename socdk board file to socdk_sdmmc

From: Dinh Nguyen Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10

[PATCH 1/3] clk: socfpga: update clk.h so for Arria10 platform to use

From: Dinh Nguyen There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate.c | 4 drivers/clk/socfpga/clk.h | 6 +- 2

[PATCH 6/7] ARM: socfpga: remove the need to map uart_io_desc

From: Dinh Nguyen All the necessary debug uart mapping is already being done in debug_ll_io_init, there's no need for it here. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 9 - 1 file changed, 9 deletions(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/m

[PATCH 3/3] ARM: socfpga: dts: add clocks to the Arria10 platform

From: Dinh Nguyen Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 298 - 1 file changed, 294 insertions(+),

[PATCH 5/7] ARM: socfpga: Add support for UART1 debug uart for earlyprintk

From: Dinh Nguyen Add support for hardware uart1 for earlyprintk support on Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig.debug | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index

[PATCH 2/7] ARM: socfpga: disable the sdmmc, and uart nodes in the base arria10

From: Dinh Nguyen Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/socf

[PATCH 1/7] ARM: socfpga: add cpu1-start-addr for Arria 10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8a05c47..69d616a 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi

[PATCHv2 net-next] net: stmmac: make reset control an optional requirement

From: Dinh Nguyen Not having a reset control line to the ethernet controller should not be a hard failure. Instead, add support for deferred probing and just print out a debug statement. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers CC: David S. Miller --- v2: return EPROBE_DEFER directly as

[PATCH] net: stmmac: make reset control an optional requirement

From: Dinh Nguyen Not having a reset control line to the ethernet controller should not be a hard failure. Instead, add support for deferred probing and just print out a debug statement. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers CC: David S. Miller --- drivers/net/ethernet/stmicro/stmmac

[RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

From: Dinh Nguyen By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel

[RESEND PATCH 1/2] arm: socfpga: update l2 cache settings

From: Dinh Nguyen Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga

[RFC PATCH] arm: cti: fix up cti pmu build

From: Dinh Nguyen commit "184901a06a36 ARM: removing support for etb/etm in "arch/arm/kernel/" removed arch/arm/include/asm/hardware/coresight.h then commit "a06ae8609b3d coresight: add CoreSight core layer framework" added include/linux/coresight.h Update cti.h to use thew new coresight.h and

[RFC PATCH] arm: cti: fix build for cti.h

From: Dinh Nguyen Hi, I would to like check to see if this is right thing to do for cti.h. Our downstream kernel's PMU support is using cti.h. But I don't see any other upstream driver using cti.h, so I'm not sure if this file should be removed? Thanks, Dinh Nguyen (1): arm: cti: fix up cti

[PATCH] mtd: denali: Disable sub-page writes in Denali NAND driver

From: Graham Moore The Denali Controller IP does not support sub-page writes. Signed-off-by: Graham Moore Signed-off-by: Dinh Nguyen --- drivers/mtd/nand/denali.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index b3b7ca1..b16b04

[PATCH] mtd: denali: fix incorrect bitmask error in denali_setup_dma

From: Graham Moore commit "3157d1ed2309 mtd: denali: remove unnecessary casts" introduced an error by using a wrong bitmask. A uint16_t cast was replaced with & 0xff, should be & 0x. Signed-off-by: Graham Moore Signed-off-by: Dinh Nguyen --- drivers/mtd/nand/denali.c |2 +- 1 file ch

[PATCH] stmmac: platform: fix stmmac probe failure

From: Dinh Nguyen The commit 571dcfde23712b ("stmmac: platform: fix default values of the filter bins setting") broke support for stmmac probe for all CONFIG_OF platforms. [0.743567] Unable to handle kernel NULL pointer dereference at virtual address 0048 [0.751679] pgd = c0004000 [

[PATCH] usb: dwc2: remove early return on clock query

From: Dinh Nguyen Since we have assigned clk=NULL, which is a valid clk, we should not be returning when a clock node is not provide. Instead, we should return only when we cannot enable the clock. Signed-off-by: Dinh Nguyen --- drivers/usb/dwc2/gadget.c | 10 +++--- 1 file changed, 7 inse

[PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

From: Dinh Nguyen By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel

[PATCH 1/2] arm: socfpga: update l2 cache settings

From: Dinh Nguyen Enable D and I prefetch helps improve SDRAM preformance. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index adbf383..13b18

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