On Mon, Jul 27, 2020 at 3:01 PM Dmitry Torokhov
wrote:
>
> On Mon, Jul 27, 2020 at 11:29:33PM +0200, Pavel Machek wrote:
> > Hi!
> >
> > > From: Derek Basehore
> > >
> > > [ Upstream commit 966334dfc472bdfa67bed864842943b19755d192 ]
> > >
> > > This moves the wakeup increment for elan devices to
On Mon, Jun 29, 2020 at 10:16 PM Dmitry Torokhov
wrote:
>
> On Mon, Jun 29, 2020 at 05:57:07PM -0700, Derek Basehore wrote:
> > This moves the wakeup increment for elan devices to the touch report.
> > This prevents the drivers from incorrectly reporting a wakeup when the
> > resume callback reset
On Mon, Jun 24, 2019 at 1:36 PM Sam Ravnborg wrote:
>
> Hi Derek.
>
> On Fri, Jun 21, 2019 at 08:41:02PM -0700, Derek Basehore wrote:
> > This adds a helper function for reading the rotation (panel
> > orientation) from the device tree.
> >
> > Signed-off-by: Derek Basehore
> > ---
> > drivers/g
On Tue, Jun 11, 2019 at 1:57 AM Daniel Vetter wrote:
>
> On Mon, Jun 10, 2019 at 09:03:48PM -0700, Derek Basehore wrote:
> > This adds the attach/detach callbacks. These are for setting up
> > internal state for the connector/panel pair that can't be done at
> > probe (since the connector doesn't
On Mon, Mar 4, 2019 at 8:49 PM Derek Basehore wrote:
>
> This changes the clk_set_rate code to use lists instead of recursion.
> While making this change, also add error handling for clk_set_rate.
> This means that errors in the set_rate/set_parent/set_rate_and_parent
> functions will not longer b
On Tue, Mar 5, 2019 at 5:35 PM dbasehore . wrote:
>
> On Tue, Mar 5, 2019 at 10:49 AM Stephen Boyd wrote:
> >
> > Quoting Derek Basehore (2019-03-04 20:49:31)
> > > From: Stephen Boyd
> > >
> > > Enabling and preparing clocks can be written quite nat
On Tue, Mar 5, 2019 at 10:49 AM Stephen Boyd wrote:
>
> Quoting Derek Basehore (2019-03-04 20:49:31)
> > From: Stephen Boyd
> >
> > Enabling and preparing clocks can be written quite naturally with
> > recursion. We start at some point in the tree and recurse up the
> > tree to find the oldest pa
On Thu, Dec 20, 2018 at 1:15 PM Stephen Boyd wrote:
>
> Quoting Derek Basehore (2018-10-23 18:31:26)
> > Here's the first set of patches that I'm working on for the Common
> > Clk Framework. Part of this patch series adds a new clk op,
> > pre_rate_req. This is designed to replace the clk notifier
On Wed, Dec 12, 2018 at 1:09 AM Peter Zijlstra wrote:
>
> On Tue, Dec 11, 2018 at 06:25:06PM -0800, Derek Basehore wrote:
> > The function __lock_acquire checks that the nest lock is held passed
> > in as an argument. The issue with this is that __lock_acquire is used
> > for internal bookkeeping
On Mon, Nov 19, 2018 at 1:41 AM Heiko Stübner wrote:
>
> Am Freitag, 16. November 2018, 19:23:59 CET schrieb Doug Anderson:
> > Hi,
> >
> > On Fri, Nov 16, 2018 at 9:39 AM dbasehore . wrote:
> > > On Fri, Nov 16, 2018 at 8:01 AM Doug Anderson
> wrote:
> &
On Fri, Nov 16, 2018 at 8:01 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Nov 15, 2018 at 9:17 PM Derek Basehore wrote:
> >
> > This adds the xin32k clock to the RK3399 CPU. Even though it's not
> > directly used, muxes will end up traversing the entire clk tree on
> > calls to determine_rate if i
On Thu, Nov 15, 2018 at 9:03 PM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Nov 15, 2018 at 4:42 PM Derek Basehore wrote:
> >
> > This adds the xin32k clock to the RK3399 CPU. Even though it's not
> > directly used, muxes will end up traversing the entire clk tree on
> > calls to determine_rate if i
On Fri, Aug 31, 2018 at 2:20 PM Derek Basehore wrote:
>
> clk_calc_subtree was called at every step up the clk tree in
> clk_calc_new_rates. Since it recursively calls itself for its
> children, this means it would be called once on each clk for each
> step above the top clk is.
>
> This is fixed
On Mon, Aug 27, 2018 at 4:52 AM Andi Shyti wrote:
>
> Hi Derek,
>
> next time, could you please avoid using html mails when replying
> to the mailing list? They are not clear.
Sorry, my plain text setting was reset for some reason.
>
> On Fri, Aug 24, 2018 at 04:07:41PM -07
On Fri, Aug 24, 2018 at 4:07 PM dbasehore . wrote:
>
>
>
> On Fri, Aug 24, 2018 at 1:49 AM Andi Shyti wrote:
>>
>> Hi Derek,
>>
>> > > > On Thu, Aug 23, 2018 at 04:10:13PM -0700, Derek Basehore wrote:
>> > > > > We onl
On Fri, Jul 27, 2018 at 5:07 AM Hans de Goede wrote:
> Hi,
>
> On 07/27/2018 12:44 PM, Andy Shevchenko wrote:
> > On Fri, Jul 27, 2018 at 1:55 AM, Derek Basehore
> wrote:
> >> This enables the async suspend property for i2c devices. This reduces
> >> the suspend/resume time considerably on platf
On Wed, Mar 14, 2018 at 2:44 PM, dbasehore . wrote:
> On Wed, Mar 14, 2018 at 3:22 AM, Marc Zyngier wrote:
>> On 02/03/18 02:08, dbasehore . wrote:
>>> On Thu, Mar 1, 2018 at 4:29 AM, Marc Zyngier wrote:
>>>> Hi Mark,
>>>>
>>>> On 01/03/18
On Wed, Mar 14, 2018 at 3:22 AM, Marc Zyngier wrote:
> On 02/03/18 02:08, dbasehore . wrote:
>> On Thu, Mar 1, 2018 at 4:29 AM, Marc Zyngier wrote:
>>> Hi Mark,
>>>
>>> On 01/03/18 11:41, Mark Rutland wrote:
>>>> On Wed, Feb 28, 2018 at 09
On Thu, Mar 1, 2018 at 12:39 AM, Sebastian Andrzej Siewior
wrote:
> On 2018-02-28 19:27:54 [-0800], Derek Basehore wrote:
>> If cpu_cluster_pm_enter() fails, cpu_pm_exit() should be called. This
>> will put the CPU in the correct state to resume from the failure.
>
> Was this triggered or found on
On Thu, Mar 1, 2018 at 4:29 AM, Marc Zyngier wrote:
> Hi Mark,
>
> On 01/03/18 11:41, Mark Rutland wrote:
>> On Wed, Feb 28, 2018 at 09:48:18PM -0800, Derek Basehore wrote:
>>> Some platforms power off GIC logic in suspend, so we need to
>>> save/restore state. The distributor and redistributor re
On Wed, Feb 7, 2018 at 1:21 AM, Marc Zyngier wrote:
> On 07/02/18 01:41, Derek Basehore wrote:
>> This adds documentation for the new reset-on-suspend property. This
>> property enables saving and restoring the ITS for when it loses state
>> in system suspend.
>>
>> Signed-off-by: Derek Basehore
On Wed, Feb 7, 2018 at 3:22 PM, Brian Norris wrote:
> Hi Marc,
>
> I'm really not an expert on this, so take my observations with a large
> grain of salt:
>
> On Wed, Feb 07, 2018 at 08:46:42AM +, Marc Zyngier wrote:
>> On 07/02/18 01:41, Derek Basehore wrote:
>> > This adds functionality to r
On Tue, Feb 6, 2018 at 8:23 AM, Marc Zyngier wrote:
> On 05/02/18 21:33, dbasehore . wrote:
>> On Mon, Feb 5, 2018 at 7:56 AM, Marc Zyngier wrote:
>>> On 03/02/18 01:24, Derek Basehore wrote:
>>>> Some platforms power off GIC logic in suspend, so we need t
On Tue, Feb 6, 2018 at 8:40 AM, Marc Zyngier wrote:
> On 03/02/18 01:24, Derek Basehore wrote:
>> This adds functionality to resend the MAPC command to an ITS node on
>> resume. If the ITS is powered down during suspend and the collections
>> are not backed by memory, the ITS will lose that state.
On Mon, Feb 5, 2018 at 5:01 PM, dbasehore . wrote:
> On Mon, Feb 5, 2018 at 4:33 PM, dbasehore . wrote:
>> On Mon, Feb 5, 2018 at 7:56 AM, Marc Zyngier wrote:
>>> On 03/02/18 01:24, Derek Basehore wrote:
>>>> Some platforms power off GIC logic in suspend, so we n
On Mon, Feb 5, 2018 at 4:33 PM, dbasehore . wrote:
> On Mon, Feb 5, 2018 at 7:56 AM, Marc Zyngier wrote:
>> On 03/02/18 01:24, Derek Basehore wrote:
>>> Some platforms power off GIC logic in suspend, so we need to
>>> save/restore state. The distributor and redistribut
On Mon, Feb 5, 2018 at 7:56 AM, Marc Zyngier wrote:
> On 03/02/18 01:24, Derek Basehore wrote:
>> Some platforms power off GIC logic in suspend, so we need to
>> save/restore state. The distributor and redistributor registers need
>> to be handled in platform code due to access permissions on thos
On Mon, Feb 5, 2018 at 7:56 AM, Marc Zyngier wrote:
> On 03/02/18 01:24, Derek Basehore wrote:
>> Some platforms power off GIC logic in suspend, so we need to
>> save/restore state. The distributor and redistributor registers need
>> to be handled in platform code due to access permissions on thos
On Mon, Jan 29, 2018 at 5:00 PM, Derek Basehore wrote:
> Some platforms power off GIC logic in suspend, so we need to
> save/restore state. The distributor and redistributor registers need
> to be handled in platform code due to access permissions on those
> registers, but the ITS registers can be
On Mon, Jan 29, 2018 at 5:00 PM, Derek Basehore wrote:
> This adds functionality to resend the MAPC command to an ITS node on
> resume. If the ITS is powered down during suspend and the collections
> are not backed by memory, the ITS will lose that state. This just sets
> up the known state for th
On Fri, Jan 26, 2018 at 12:59 PM, Brian Norris wrote:
> One trivial comment:
>
> On Thu, Jan 25, 2018 at 11:38:32PM -0800, Derek Basehore wrote:
>> Some platforms power off GIC logic in suspend, so we need to
>> save/restore state. The distributor and redistributor registers need
>> to be handled
On Sun, Jan 14, 2018 at 2:56 AM, Marc Zyngier wrote:
> On Fri, 12 Jan 2018 21:24:20 +,
> Derek Basehore wrote:
>>
>> This adds a DT-binding to resend the MAPC command to an ITS node on
>
> This isn't a DT binding. That's the driver implementation. The binding
> is what you put in Documentation
On Fri, Jan 19, 2018 at 1:22 AM, Marc Zyngier wrote:
> On 18/01/18 23:33, Brian Norris wrote:
>> Hi,
>>
>> On Sat, Jan 13, 2018 at 06:10:52PM +, Marc Zyngier wrote:
>>> On Fri, 12 Jan 2018 21:24:18 +,
>>> Derek Basehore wrote:
Some platforms power off GIC logic in S3, so we need
On Thu, Nov 30, 2017 at 1:44 AM, Marc Zyngier wrote:
> On Wed, Nov 29 2017 at 2:49:18 pm GMT, "dbasehore ."
> wrote:
>> There was some work in ARM Trusted Firmware to support saving and
>> restoring the Generic Interrupt Controller (GICv3) before and after
>>
There was some work in ARM Trusted Firmware to support saving and
restoring the Generic Interrupt Controller (GICv3) before and after
sleep, but it seems that the plan is to have this all in the kernel
now. The point of doing this is to save power during sleep. On an
RK3399 system, we save about 15
Okay, I think that this is just my email client confusing me. Please
ignore this email and just review the first "PATCH v2" patch.
Did not mean to send this in-reply to. It seems that git send-email
was not applying my "PATCH v2" prefix. Will resend as a separate
thread.
On Tue, Aug 29, 2017 at 7:05 AM, Thierry Reding
wrote:
> On Mon, Aug 28, 2017 at 01:00:33PM -0700, Derek Basehore wrote:
>> This fixes and overflow condition that happens with a high value of
>> brightness-levels-scale by using a 64-bit variable. The issue would
>> prevent a range of higher bright
On Tue, Jul 18, 2017 at 3:22 PM, Thomas Gleixner wrote:
> On Tue, 18 Jul 2017, dbasehore . wrote:
>> On Tue, Jul 18, 2017 at 2:53 PM, Thomas Gleixner wrote:
>> > On Tue, 18 Jul 2017, dbasehore . wrote:
>> >> On Mon, Jul 17, 2017 at 11:40 PM, Thomas Gleixner
>&
On Tue, Jul 18, 2017 at 2:53 PM, Thomas Gleixner wrote:
> On Tue, 18 Jul 2017, dbasehore . wrote:
>> On Mon, Jul 17, 2017 at 11:40 PM, Thomas Gleixner wrote:
>> > On Mon, 17 Jul 2017, dbasehore . wrote:
>> >> On Mon, Jul 17, 2017 at 6:33 PM, Rafael J. Wysocki
>
On Mon, Jul 17, 2017 at 11:40 PM, Thomas Gleixner wrote:
> On Mon, 17 Jul 2017, dbasehore . wrote:
>> On Mon, Jul 17, 2017 at 6:33 PM, Rafael J. Wysocki wrote:
>> I could make a patch to try it out. I would probably add a flag to rtc
>> timers to indicate whether it wake
On Mon, Jul 17, 2017 at 6:33 PM, Rafael J. Wysocki wrote:
> On Tue, Jul 18, 2017 at 2:30 AM, dbasehore . wrote:
>> On Sat, Jul 15, 2017 at 5:39 AM, Rafael J. Wysocki
>> wrote:
>>> On Thursday, July 13, 2017 03:58:53 PM dbasehore . wrote:
>>>> On Thu, Jul 13
On Sat, Jul 15, 2017 at 5:39 AM, Rafael J. Wysocki wrote:
> On Thursday, July 13, 2017 03:58:53 PM dbasehore . wrote:
>> On Thu, Jul 13, 2017 at 8:09 AM, Rafael J. Wysocki wrote:
>> > On Thu, Jul 13, 2017 at 9:32 AM, Peter Zijlstra
>> > wrote:
>> >> O
On Thu, Jul 13, 2017 at 8:09 AM, Rafael J. Wysocki wrote:
> On Thu, Jul 13, 2017 at 9:32 AM, Peter Zijlstra wrote:
>> On Fri, Jul 07, 2017 at 05:03:00PM -0700, Derek Basehore wrote:
>>> Adds a new feature to tick to schedule wakeups on a CPU during freeze.
>>> This won't fully wake up the system
On Wed, Jul 12, 2017 at 10:11 PM, Thomas Gleixner wrote:
> On Wed, 12 Jul 2017, dbasehore . wrote:
>> On Wed, Jul 12, 2017 at 3:16 PM, Thomas Gleixner wrote:
>> > There are more issues with this: If there is a hrtimer scheduled on that
>> > last CPU which enters the
On Wed, Jul 12, 2017 at 2:25 PM, Thomas Gleixner wrote:
> On Fri, 7 Jul 2017, Derek Basehore wrote:
>> Adds a new feature to tick to schedule wakeups on a CPU during freeze.
>> This won't fully wake up the system (devices are not resumed), but
>> allow simple platform functionality to be run durin
On Wed, Jul 12, 2017 at 3:16 PM, Thomas Gleixner wrote:
> On Fri, 7 Jul 2017, Derek Basehore wrote:
>> This adds validation of S0ix entry and enables it on Skylake. Using
>> the new tick_set_freeze_event function, we program the CPU to wake up
>> X seconds after entering freeze. After X seconds, i
On Wed, Jul 12, 2017 at 3:16 PM, Thomas Gleixner wrote:
> On Fri, 7 Jul 2017, Derek Basehore wrote:
>> This adds validation of S0ix entry and enables it on Skylake. Using
>> the new tick_set_freeze_event function, we program the CPU to wake up
>> X seconds after entering freeze. After X seconds, i
On Mon, Jul 10, 2017 at 3:09 PM, Rafael J. Wysocki wrote:
> On Monday, July 10, 2017 02:57:48 PM dbasehore . wrote:
>> On Mon, Jul 10, 2017 at 6:33 AM, Rafael J. Wysocki
>> wrote:
>> > On Friday, July 07, 2017 05:03:03 PM Derek Basehore wrote:
>> >> Th
On Mon, Jul 10, 2017 at 6:33 AM, Rafael J. Wysocki wrote:
> On Friday, July 07, 2017 05:03:03 PM Derek Basehore wrote:
>> This adds validation of S0ix entry and enables it on Skylake. Using
>> the new tick_set_freeze_event function, we program the CPU to wake up
>> X seconds after entering freeze.
On Sat, Jul 8, 2017 at 9:05 AM, Andy Shevchenko
wrote:
> On Sat, Jul 8, 2017 at 3:03 AM, Derek Basehore wrote:
>> Adds a new feature to tick to schedule wakeups on a CPU during freeze.
>> This won't fully wake up the system (devices are not resumed), but
>> allow simple platform functionality to
On Wed, Sep 7, 2016 at 1:31 PM, Sean Paul wrote:
> On Wed, Sep 7, 2016 at 2:13 PM, dbasehore . wrote:
>> On Tue, Sep 6, 2016 at 10:18 AM, Sean Paul wrote:
>>> On Mon, Sep 5, 2016 at 1:06 AM, Lin Huang wrote:
>>>> when in ddr frequency scaling process, vop can
On Tue, Sep 6, 2016 at 10:18 AM, Sean Paul wrote:
> On Mon, Sep 5, 2016 at 1:06 AM, Lin Huang wrote:
>> when in ddr frequency scaling process, vop can not do enable or
>> disable operation, since in dcf we check vop clock to see whether
>> vop work. If vop work, dcf do ddr frequency scaling when
On Tue, Sep 6, 2016 at 12:07 PM, Sean Paul wrote:
> On Tue, Sep 6, 2016 at 3:01 PM, hl wrote:
>> Hi
>>
>>
>> On 2016年09月07日 02:55, Sean Paul wrote:
>>>
>>> On Tue, Sep 6, 2016 at 2:15 PM, hl wrote:
Hi Sean,
On 2016年09月07日 01:18, Sean Paul wrote:
>
> On Mon, Sep 5
On Thu, Jun 9, 2016 at 3:43 PM, Thomas Gleixner wrote:
> On Thu, 9 Jun 2016, dbaseh...@chromium.org wrote:
>>
>> +/*
>> + * Clockevent device may run during freeze
>> + */
>> +# define CLOCK_EVT_FEAT_FREEZE 0x000100
>
> This is a bad name and a horrible comment. The device does not f
From: Derek Basehore
This creates an inline function of intel_pmc_slp_s0_counter_read for
!CONFIG_INTEL_PMC_CORE.
Signed-off-by: Derek Basehore
---
arch/x86/include/asm/pmc_core.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x8
From: Derek Basehore
Adds a new feature to clockevents to schedule wakeups on a CPU during
freeze. These won't fully wake up the system, but allow simple
platform callbacks that don't require device support to be run during
freeze with little power impact.
This implementation allows an idle driv
From: Derek Basehore
This adds validation of S0ix entry and enables it on Skylake. Using
the new timed_freeze function, we program the CPU to wake up X seconds
after entering freeze. After X seconds, it will wake the CPU to check
the S0ix residency counters and make sure we entered the lowest pow
From: Derek Basehore
This adds error reporting for cpuidle to freeze so suspend-to-idle can
report errors when the CPU/SoC is unable to idle properly. Freeze will
abort when an error is encounted.
Signed-off-by: Derek Basehore
---
drivers/acpi/processor_idle.c | 10 ++
drivers/cpuidle/
From: Derek Basehore
This adds support to the clock event devices created by apic to use
timed freeze. The apic is able to run a timer during freeze with near
izero impact on modern CPUs such as skylake. This will allow S0ix,
suspend-to-idle, to be validated on Intel CPUs that support it.
This i
From: Derek Basehore
This patch set adds support for catching errors when entering freeze
on Intel Skylake SoCs. Support for this can be added to newer SoCs in
later patches.
Verification is done by waking up the CPU up to 1000 seconds later
based on base 10 exponential backoff from 1 second to
From: Derek Basehore
Adds a new feature to clockevents to schedule wakeups on a CPU during
freeze. These won't fully wake up the system, but allow simple
platform callbacks that don't require device support to be run during
freeze with little power impact.
This implementation allows an idle driv
From: Derek Basehore
This adds support to the clock event devices created by apic to use
timed freeze. The apic is able to run a timer during freeze with near
izero impact on modern CPUs such as skylake. This will allow S0ix,
suspend-to-idle, to be validated on Intel CPUs that support it.
This i
From: Derek Basehore
This adds error reporting for cpuidle to freeze so suspend-to-idle can
report errors when the CPU/SoC is unable to idle properly. Freeze will
abort when an error is encounted.
Signed-off-by: Derek Basehore
---
drivers/acpi/processor_idle.c | 10 ++
drivers/cpuidle/
From: Derek Basehore
This patch set adds support for catching errors when entering freeze
on Intel Skylake SoCs. Support for this can be added to newer SoCs in
later patches.
Verification is done by waking up the CPU up to 1000 seconds later
based on base 10 exponential backoff from 1 second to
From: Derek Basehore
This adds validation of S0ix entry and enables it on Skylake. Using
the new timed_freeze function, we program the CPU to wake up X seconds
after entering freeze. After X seconds, it will wake the CPU to check
the S0ix residency counters and make sure we entered the lowest pow
From: Derek Basehore
This creates an inline function of intel_pmc_slp_s0_counter_read for
!CONFIG_INTEL_PMC_CORE.
Signed-off-by: Derek Basehore
---
arch/x86/include/asm/pmc_core.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x8
From: Derek Basehore
This adds validation of S0ix entry and enables it on Skylake. Using
the new timed_freeze function, we program the CPU to wake up X seconds
after entering freeze. After X seconds, it will wake the CPU to check
the S0ix residency counters and make sure we entered the lowest pow
From: Derek Basehore
This adds support to the clock event devices created by apic to use
timed freeze. The apic is able to run a timer during freeze with near
izero impact on modern CPUs such as skylake. This will allow S0ix,
suspend-to-idle, to be validated on Intel CPUs that support it.
This i
From: Derek Basehore
This patch set adds support for catching errors when entering freeze
on Intel Skylake SoCs. Support for this can be added to newer SoCs in
later patches.
Verification is done by waking up the CPU up to 1000 seconds later
based on base 10 exponential backoff from 1 second to
From: Derek Basehore
Adds a new feature to clockevents to schedule wakeups on a CPU during
freeze. These won't fully wake up the system, but allow simple
platform callbacks that don't require device support to be run during
freeze with little power impact.
This implementation allows an idle driv
From: Derek Basehore
This adds error reporting for cpuidle to freeze so suspend-to-idle can
report errors when the CPU/SoC is unable to idle properly. Freeze will
abort when an error is encounted.
Signed-off-by: Derek Basehore
---
drivers/acpi/processor_idle.c | 10 ++
drivers/cpuidle/
From: Derek Basehore
This creates an inline function of intel_pmc_slp_s0_counter_read for
!CONFIG_INTEL_PMC_CORE.
Signed-off-by: Derek Basehore
---
arch/x86/include/asm/pmc_core.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x8
On Tue, Jun 7, 2016 at 12:46 AM, Pavel Machek wrote:
> On Wed 2016-06-01 21:33:24, dbaseh...@chromium.org wrote:
>> From: Derek Basehore
>>
>> This patch set adds support for catching errors when entering freeze
>> on Intel Skylake SoCs. Support for this can be added to newer SoCs in
>> later pat
On Sat, Jun 4, 2016 at 5:22 AM, Alan wrote:
>> I would expect those IP blocks to do nothing and not block lower power
>> states if the firmware is not loaded. If that is not the case, I think
>> that should be fixed such that those lower power states are at least
>> available during suspend (if no
On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang wrote:
> when in ddr frequency scaling process, vop can not do
> enable or disable operate, since dcf will base on vop vblank
> time to do frequency scaling and need to get vop irq if there
> have vop enabled. So need register to dmc notifier, and we can
>
On Thu, Jun 2, 2016 at 12:53 PM, One Thousand Gnomes
wrote:
>> How would this spuriously trigger during boot? This code is only run
>> during freeze. If there's some issue with not entering S0ix before a
>> module or firmware is loaded, it's better to not use suspend to idle
>> until those are in
On Thu, Jun 2, 2016 at 6:23 AM, One Thousand Gnomes
wrote:
>
> There are plenty of Skylake configurations where at the moment you won't
> get s0ix entry because the ISH driver is not yet merged. Spamming those
> users with useless messages is not helpful. Likewise on systems with
> modular kernels
On Thu, Jun 2, 2016 at 6:23 AM, One Thousand Gnomes
wrote:
> On Thu, 2 Jun 2016 11:25:05 +0200
> Peter Zijlstra wrote:
>
>> On Wed, Jun 01, 2016 at 09:33:29PM -0700, dbaseh...@chromium.org wrote:
>> > +/*
>> > + * Default chosen to have <= 1% power increase while allowing fast
>> > detection of
From: Derek Basehore
This adds error reporting for cpuidle to freeze so suspend-to-idle can
report errors when the CPU/SoC is unable to idle properly. Freeze will
abort when an error is encounted.
Signed-off-by: Derek Basehore
---
drivers/acpi/processor_idle.c | 10 ++
drivers/cpuidle/
From: Derek Basehore
This adds support to the clock event devices created by apic to use
timed freeze. The apic is able to run a timer during freeze with near
izero impact on modern CPUs such as skylake. This will allow S0ix,
suspend-to-idle, to be validated on Intel CPUs that support it.
This i
From: Derek Basehore
Adds a new feature to clockevents to schedule wakeups on a CPU during
freeze. These won't fully wake up the system, but allow simple
platform callbacks that don't require device support to be run during
freeze with little power impact.
This implementation allows an idle driv
From: Derek Basehore
This creates an inline function of intel_pmc_slp_s0_counter_read for
!CONFIG_INTEL_PMC_CORE.
Signed-off-by: Derek Basehore
---
arch/x86/include/asm/pmc_core.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x8
From: Derek Basehore
This adds validation of S0ix entry and enables it on Skylake. Using
the new timed_freeze function, we program the CPU to wake up X seconds
after entering freeze. After X seconds, it will wake the CPU to check
the S0ix residency counters and make sure we entered the lowest pow
From: Derek Basehore
This patch set adds support for catching errors when entering freeze
on Intel Skylake SoCs. Support for this can be added to newer SoCs in
later patches.
Verification is done by waking up the CPU once every X (default 10)
seconds to check the residency of S0ix. This can't be
On Thu, May 12, 2016 at 6:50 AM, Rajneesh Bhardwaj
wrote:
>
> + * pmc_dev contains info about power management controller device.
> + */
> +struct pmc_dev {
> + u32 base_addr;
> + void __iomem *regmap;
> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> + struct dentry *dbgfs_dir;
> +#endif /*
On Sat, Feb 27, 2016 at 5:31 PM, Rafael J. Wysocki wrote:
> On Wednesday, February 24, 2016 04:22:27 PM Derek Basehore wrote:
>> This tries to runtime suspend devices that are still active for direct
>> complete. This is for cases such as autosuspend delays which leaves
>> devices able to runtime
On Sat, Feb 27, 2016 at 12:38 AM, Mika Westerberg
wrote:
> On Sat, Feb 27, 2016 at 12:10:03AM -0800, dbasehore . wrote:
>> A device is not able to use direct complete if its children do not
>> also use direct complete. Even though the SCSI layer leaves devices
>> runtime
A device is not able to use direct complete if its children do not
also use direct complete. Even though the SCSI layer leaves devices
runtime suspended, the way it does it still prevents its parent from
using direct complete.
On Fri, Feb 26, 2016 at 11:26 PM, Mika Westerberg
wrote:
> On Wed, Feb
On Tue, Jan 5, 2016 at 4:48 AM, Rafael J. Wysocki wrote:
> On Monday, January 04, 2016 06:27:18 PM Derek Basehore wrote:
>> On Mon, Nov 02, 2015 at 02:50:40AM +0100, Rafael J. Wysocki wrote:
>> >
>> > I've queued up this series for the second half of the v4.4 merge window.
>> >
>> > Thanks,
>> > R
fael J. Wysocki wrote:
> On Thursday, October 02, 2014 12:25:08 AM Rafael J. Wysocki wrote:
>> On Wednesday, October 01, 2014 01:48:39 PM dbasehore . wrote:
>> > Adding maintainers for affected systems to this CL for review.
>> >
>> > On Mon, Jul 7, 2014 at 8:33 A
Adding maintainers for affected systems to this CL for review.
On Mon, Jul 7, 2014 at 8:33 AM, Konrad Rzeszutek Wilk
wrote:
> On Fri, Jun 27, 2014 at 05:04:24PM -0700, Derek Basehore wrote:
>> In the case of a late abort to suspend/hibernate, irqs marked with
>> IRQF_EARLY_RESUME will not be enab
Based on what Thomas pointed out and my own thoughts, as long as we don't
plan on changing the rate of the safe parent, but changing our own dividers, we
should be able to use set_rate_and_parent to solve the issue on Samsung's
SoCs. If we can think of a reason that we might need to change the rate
This is a regression introduced in "ACPI / TPM: match node name
instead of full path when searching for TPM device" which was authored
on December 19, 2013.
On Wed, May 7, 2014 at 11:09 PM, Peter Huewe wrote:
> Hi Derek,
> Is this a regression?
> Do you know since when?
> Thanks
> Peter
> ---
> S
On Mon, Mar 17, 2014 at 7:40 AM, Tejun Heo wrote:
> Hello,
>
> On Sun, Mar 16, 2014 at 12:13:55PM -0700, dbasehore . wrote:
>> There's already behavior that is somewhat like that with the current
>> implementation. If there's an item on a workqueue, it cou
Also, the difference it would make is fix the issue for when a
delayed_work is used for both immediate work (mod_delayed_work(0)) and
delayed work.
On Sun, Mar 16, 2014 at 12:13 PM, dbasehore . wrote:
> There's already behavior that is somewhat like that with the current
> impleme
queue).
On Sun, Mar 16, 2014 at 7:59 AM, Tejun Heo wrote:
> On Sat, Mar 15, 2014 at 01:22:53PM -0700, dbasehore . wrote:
>> mod_delayed_work currently removes a work item from a workqueue if it
>> is on it. Correct me if I'm wrong, but I don't think that this is
>> nec
Resurrecting this for further discussion about the root of the problem.
mod_delayed_work_if_later addresses the problem one way, but the
problem is still there for mod_delayed_work. I think we could take
another approach that doesn't modify the API, but still addresses
(most of) the problem.
mod_
We haven't had any issues with this patch and we've had it in our tree
for a while.
I also stress tested the patch by repeatedly reading over the spi a lot.
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I'm still debugging all of the issues, but allowing the cmos interrupt
handler to run before resuming caused some issues where the timer for
the alarm was not removed. This would cause other, later timers to not
be cleared, so utilities such as hwclock would time out when waiting
for the update int
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