Re: [PATCH] timers: fix offset calculation when the expires align with LVL_GRAN

On 2018/7/31 22:34, Thomas Gleixner wrote: > > > On Tue, 31 Jul 2018, Thomas Gleixner wrote: > >> On Tue, 31 Jul 2018, Xu YiPing wrote: >>> On 2018/7/30 19:03, Thomas Gleixner wrote: >>>> >>>> __internal_add_timer(base,

Re: [PATCH] timers: fix offset calculation when the expires align with LVL_GRAN

On 2018/7/30 19:03, Thomas Gleixner wrote: > On Fri, 27 Jul 2018, Xu YiPing wrote: > >> when the expires of timer is align with LVL_GRAN(n), it will be trigged >> in 'expires + LVL_GRAN(n)'. >> >> Some drivers like power runtime use the timer to start a

Re: [PATCH] timers: fix offset calculation when the expires align with LVL_GRAN

On 2018/7/30 19:03, Thomas Gleixner wrote: > On Fri, 27 Jul 2018, Xu YiPing wrote: > >> when the expires of timer is align with LVL_GRAN(n), it will be trigged >> in 'expires + LVL_GRAN(n)'. >> >> Some drivers like power runtime use the timer to start a

[PATCH] timers: fix offset calculation when the expires align with LVL_GRAN

when the expires of timer is align with LVL_GRAN(n), it will be trigged in 'expires + LVL_GRAN(n)'. Some drivers like power runtime use the timer to start a power down of device, it could saves power if the timer is triggerd in time, especially when LEVEL=0 with low expires. Signed-

[PATCH v3 3/3] dts: arm64: Add mailbox binding for hi3660

From: Kaihua Zhong Add DT binding for mailbox driver. Signed-off-by: Leo Yan Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/

[PATCH v3 0/3] Add support for Hi3660 mailbox driver

From: Leo Yan Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. This patch series is to implement an initial version for Hi3660 mailbox driver with "automatic acknowledge" mode. The patch set have been verified with Hi3660 stub clock driver, so we can

[PATCH v3 2/3] mailbox: Add support for Hi3660 mailbox

From: Kaihua Zhong Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and a

[PATCH v3 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding

From: Leo Yan Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Signed-off-by: Leo Yan --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++ 1 file changed

[PATCH v3 1/3] dt-bindings: clk: Hi3660: Document stub clock

From: Leo Yan Document the DT binding for stub clock which is used for CPU, GPU and DDR frequency scaling. Acked-by: Rob Herring Signed-off-by: Leo Yan --- Documentation/devicetree/bindings/clock/hi3660-clock.txt | 6 ++ include/dt-bindings/clock/hi3660-clock.h | 7 +++

[PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks

From: Kaihua Zhong Hi3660 has four stub clocks, which are big and LITTLE cluster clocks, GPU clock and DDR clock. These clocks ask MCU for frequency scaling by sending message through mailbox. This commit adds support for stub clocks, it requests the dedicated mailbox channel at initialization;

[PATCH v3 3/3] arm64: dts: Hi3660: Add binding for stub clock

From: Kaihua Zhong Add DT binding for Hi3660 stub clock driver. Reviewed-by: Leo Yan Signed-off-by: Kai Zhao Signed-off-by: Tao Wang Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a

[PATCH v3 0/3] Add support for Hi3660 stub clock

From: Leo Yan Hi3660 has stub clocks for two CPU clusters, GPU and DDR; and the stub clocks use the mailbox to send message to MCU for frequency scaling. This patch set adds support Hi3660 stub clock, and since it needs to use mailbox so this patch set has dependency with Hi3660 mailbox patch se

[PATCH v2] arm64: perf: remove unsupported events for Cortex-A73

bus access read/write events are not supported in A73, based on the Cortex-A73 TRM r0p2, section 11.9 Events (pages 11-457 to 11-460). Fixes: 5561b6c5e981 "arm64: perf: add support for Cortex-A73" Signed-off-by: Xu YiPing --- arch/arm64/kernel/perf_event.c | 6 -- 1 file

[PATCH] arm64: perf: remove duplicated and unsupported events for Cortex-A73

bus access read/write events are not supported in A73, and the definition is duplicated, so delete it. Signed-off-by: Xu YiPing --- arch/arm64/kernel/perf_event.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index

[PATCH v2] arm64: dts: hi3660: improve pmu description

cortex-a73 pmu driver is supported now. hi3660 is 4*a73 + 4*a53, so it should use "cortex-a73-pmu" and "cortex-a53-pmu" instead of "armpmu-v3", then we can use the a73 and a53 events in perf tool directly. Signed-off-by: Xu YiPing --- arch/arm64/boot/

[PATCH] arm64: dts: hi3660: improve pmu description

cortex a73 pmu is supported, use it instead of armpmu-v3 --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 13ae69f..

[PATCH] rtc: interface: set the next alarm event appropriately

From: Xu YiPing After commit 2b2f5ff00f63 ("rtc: interface: ignore expired timers when enqueuing new timers"), the rtc_timer_enqueue will not reprogram the RTC when there is any non-expired timers in the timerqueue. If we set a RTC_TIMER between now and the next non-expired timers, i

[patch] staging: ion: use two separate locks for heaps and clients in ion_device

the heaps list, ion_destroy_client hold the lock for accessing the clients list. so, we can use two separate locks for heaps and clients, to avoid the unnecessary race. Signed-off-by: Xu YiPing --- drivers/staging/android/ion/ion.c | 37 - 1 file changed, 20 ins