> On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > > +
> > > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device
> > > > > > > > > > *dfl_dev)
> > > &g
> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > >
> On Thu, Apr 08, 2021 at 09:20:19AM +0000, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > >
> > > > > Hi Matthew,
> > > > >
> > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> &
> > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> >
> > > Hi Matthew,
> > >
> > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> matthew.gerl...@linux.intel.com wrote:
> > > > From: Matthew Gerlach
> > > >
> > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > controller. The SPI mas
> Subject: [PATCH v6 1/1] fpga: dfl: afu: harden port enable logic
>
> Port enable is not complete until ACK = 0. Change
> __afu_port_enable() to guarantee that the enable process
> is complete by polling for ACK == 0.
Looks good to me.
Acked-by: Wu Hao
Thanks
Hao
>
>
> On Wed, 3 Feb 2021, Russ Weight wrote:
>
> >
> >
> > On 2/3/21 1:28 AM, Wu, Hao wrote:
> >>> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic
> >>>
> >>> Sorry for the delay on this patch. It seemed like a lower pr
> On 2/3/21 1:01 AM, Wu, Hao wrote:
> >> Subject: [PATCH v3 1/1] fpga: dfl: afu: harden port enable logic
> >>
> >> Port enable is not complete until ACK = 0. Change
> >> __afu_port_enable() to guarantee that the enable process
> >> is complete
> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic
>
> Sorry for the delay on this patch. It seemed like a lower priority patch than
> others, since we haven't seen any issues with current products. Please my
> responses inline.
>
> On 9/17
> Subject: [PATCH v3 1/1] fpga: dfl: afu: harden port enable logic
>
> Port enable is not complete until ACK = 0. Change
> __afu_port_enable() to guarantee that the enable process
> is complete by polling for ACK == 0.
>
> Signed-off-by: Russ Weight
> ---
> v3:
> - afu_port_err_clear() changed
--- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -7,6 +7,7 @@ Authors:
> - Enno Luebbers
> - Xiao Guangrong
> - Wu Hao
> +- Xu Yilun
>
> The Device Feature List (DFL) FPGA framework (and drivers according to
> this framework) hides the ve
fe6..b8497f3 100644
> --- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -7,6 +7,7 @@ Authors:
> - Enno Luebbers
> - Xiao Guangrong
> - Wu Hao
> +- Xu Yilun
>
> The Device Feature List (DFL) FPGA framework (and drivers according to
> th
> Subject: [PATCH v5 1/2] fpga: dfl: add the userspace I/O device support for
> DFL devices
>
> This patch supports the DFL drivers be written in userspace. This is
> realized by exposing the userspace I/O device interfaces.
>
> The driver leverages the uio_pdrv_genirq, it adds the uio_pdrv_genir
> Subject: Re: [PATCH v3 2/3] fpga: dfl: add the userspace I/O device support
> for DFL devices
>
> On Fri, Dec 18, 2020 at 05:59:17AM -0800, Tom Rix wrote:
> >
> > On 12/18/20 12:05 AM, Wu, Hao wrote:
> > >> Subject: [PATCH v3 2/3] fpga: dfl: add the userspace
> Subject: Re: [PATCH v3 2/3] fpga: dfl: add the userspace I/O device support
> for DFL devices
>
> On 12/18/20 12:05 AM, Wu, Hao wrote:
> >> Subject: [PATCH v3 2/3] fpga: dfl: add the userspace I/O device support
> for
> >> DFL devices
> >>
> >>
> Subject: [PATCH v3 2/3] fpga: dfl: add the userspace I/O device support for
> DFL devices
>
> This patch supports the DFL drivers be written in userspace. This is
> realized by exposing the userspace I/O device interfaces.
>
> The driver leverages the uio_pdrv_genirq, it adds the uio_pdrv_genir
> Subject: Re: [RFC] fpga: dfl: a prototype uio driver
>
> On Sun, Dec 06, 2020 at 01:55:54PM -0800, t...@redhat.com wrote:
> > From: Tom Rix
> >
> > >From [PATCH 0/2] UIO support for dfl devices
> > https://lore.kernel.org/linux-fpga/1602828151-24784-1-git-send-email-
> yilun...@intel.com/
> >
>
> Subject: Re: [PATCH v3 2/2] fpga: dfl: look for vendor specific capability
>
> Hi Matthew,
>
> On Mon, Nov 30, 2020 at 04:45:20PM -0800,
> matthew.gerl...@linux.intel.com wrote:
> >
> >
> > On Sat, 28 Nov 2020, Wu, Hao wrote:
> >
> > > &
> > > >
> > > > > + }
> > > > > +
> > > > > + offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
> > > > > + if (offset >= len) {
> > > > > + dev_err(&pcidev->dev, "%s bad
> offset %u >= %pa\n",
> > > > > + __func__, of
> Subject: [PATCH] fpga: dfl: add missing platform_device_put in
> build_info_create_dev
>
> platform_device_put is missing when it fails to set fdev->id. Set
> a temp value to do sanity check.
will this case be covered already by build_info_free()?
Hao
>
> Fixes: 543be3d8c999 ("fpga: add devi
> On Tue, 17 Nov 2020, Wu, Hao wrote:
[...]
> >> Open discussion
> >> ===
> >> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> >> index b1b157b41942..5418e8bf2496 100644
> >> --- a/drivers/fpga/dfl-pci.c
> &
> Subject: [PATCH 1/2] fpga: dfl: refactor cci_enumerate_feature_devs()
>
> From: Matthew Gerlach
>
> In preparation of looking for dfls based on a vendor
> specific pcie capability, move code that assumes
> Bar0/offset0 as start of DFL to its own function.
>
> Signed-off-by: Matthew Gerlach
>
> > +
> > + start = pci_resource_start(pcidev, bar) + offset;
> > + len -= offset;
>
> With these code, I have the following assumption:
>
> 1. There is only one DFL in one bar, multiple DFLs requires multiple
> bars.
>
> 2. The DFL region is from the "offset" to the end of t
> Subject: [PATCH 2/2] fpga: dfl: look for vendor specific capability
>
> From: Matthew Gerlach
>
> A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
> specific capability can be used to specify the start of a
> number of DFLs.
>
> Signed-off-by: Matthew Gerlach
> ---
> Documentation/f
> Subject: [RFC PATCH 3/6] fpga: dfl: add an API to get the base device for dfl
> device
>
> This patch adds an API for dfl devices to find which physical device
> owns the DFL.
>
> This patch makes preparation for supporting DFL Ether Group private
> feature driver. It uses this information to d
> Subject: [RFC PATCH 2/6] fpga: dfl: export network configuration info for DFL
> based FPGA
>
> This patch makes preparation for supporting DFL Ether Group private
> feature driver, which reads bitstream_id.vendor_net_cfg field to
> determin the interconnection of network components on FPGA devic
> Subject: [PATCH v5 1/7] fpga: sec-mgr: intel fpga security manager class
> driver
>
> Create the FPGA Security Manager class driver. The security
> manager provides interfaces to manage secure updates for the
> FPGA and BMC images that are stored in FLASH. The driver can
> also be used to update
> On Fri, Oct 16, 2020 at 09:21:50AM -0700, Tom Rix wrote:
> >
> > On 10/15/20 11:02 PM, Xu Yilun wrote:
> > > Add support for overriding the default matching of a dfl device to a dfl
> > > driver. It follows the same way that can be used for PCI and platform
> > > devices. This patch adds the 'dri
> Subject: [PATCH v2 4/7] fpga: sec-mgr: expose sec-mgr update errors
>
> Extend Intel Security Manager class driver to include
> an update/error sysfs node that can be read for error
> information when a secure update fails.
>
> Signed-off-by: Russ Weight
> ---
> v2:
> - Bumped documentation
> Subject: [PATCH v2 3/7] fpga: sec-mgr: expose sec-mgr update status
>
> Extend the Intel Security Manager class driver to
> include an update/status sysfs node that can be polled
> and read to monitor the progress of an ongoing secure
> update. Sysfs_notify() is used to signal transitions
> betw
> -Original Message-
> From: Russ Weight
> Sent: Saturday, October 3, 2020 6:37 AM
> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun ;
> Wu, Hao ; Gerlach, Matthew
> ; Weight
> Subject: [PATCH v2 1/7] fpga: sec-mgr: intel fpga security manager class
> driver
>
> Create the Intel Security Manager class driver. The security
> manager provides interfaces to manage secure updates for the
> FPGA and BMC images that are stored in FLASH. The driver can
> also be used to updat
> Subject: [PATCH 01/10] fpga: fpga-mgr: Add devm_fpga_mgr_register() API
>
> Add a devm_fpga_mgr_register() API that can be used to register a FPGA
> Manager that was created using devm_fpga_mgr_create().
>
> Introduce a struct fpga_mgr_devres that makes the devres
> allocation a little bit more
> Subject: [PATCH -next] fpga: dfl: simplify the return expression of
> fme_perf_pmu_register
>
> Simplify the return expression.
>
> Signed-off-by: Liu Shixin
Looks good to me.
Acked-by: Wu Hao
Thanks
Hao
> ---
> drivers/fpga/dfl-fme-perf.c | 7 +--
>
> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic
>
> On Thu, Sep 17, 2020 at 01:28:22PM -0700, Tom Rix wrote:
> >
> > On 9/17/20 11:32 AM, Russ Weight wrote:
> > > Port enable is not complete until ACK = 0. Change
> > > __afu_port_enable() to guarantee that the enable process
> -Original Message-
> From: Russ Weight
> Sent: Friday, September 18, 2020 2:32 AM
> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun ;
> Wu, Hao ; Gerlach, Matthew
> ; Weight
We also
> > made the similar fix for the type field.
> >
> > Signed-off-by: Xu Yilun
Acked-by: Wu Hao
Thanks
Hao
> > ---
> > drivers/fpga/dfl.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/fpga/d
> Subject: [PATCH] memory: dfl-emif: add the DFL EMIF private feature driver
>
> This driver is for the EMIF private feature implemented under FPGA
> Device Feature List (DFL) framework. It is used to expose memory
> interface status information as well as memory clearing control.
>
> The purpose
> Subject: [PATCH v1 00/12] Intel FPGA Security Manager Class Driver
>
>
> These patches depend on the patchset: "add regmap-spi-avmm & Intel
> Max10 BMC chip support" which is currently under review.
>
>--
>
> This patchset introduces
> On 9/4/20 5:23 PM, Moritz Fischer wrote:
> > Hi Russ,
> >
> > On Fri, Sep 04, 2020 at 04:52:54PM -0700, Russ Weight wrote:
> >> Create the Intel Security Manager class driver. The security
> >> manager provides interfaces to manage secure updates for the
> >> FPGA and BMC images that are stored i
Nios firmware version.
>
> For SPI part, this driver adds a spi-altera platform device as well as
> the MAX10 BMC spi slave info. A spi-altera driver will be matched to
> handle the following SPI work.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Signed-off-by: Matt
ivers/fpga/dfl-n3000-nios.c
> > > new file mode 100644
> > > index 000..aeac224
> > > --- /dev/null
> > > +++ b/drivers/fpga/dfl-n3000-nios.c
> > > @@ -0,0 +1,528 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
Nios firmware version.
>
> For SPI part, this driver adds a spi-altera platform device as well as
> the MAX10 BMC spi slave info. A spi-altera driver will be matched to
> handle the following SPI work.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Signed-off-by: Matt
ndled by separate driver modules.
>
> DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on
> enumeration. DFL drivers could be registered on this bus to match these
> DFL devices. They are matched by dfl type & feature_id.
>
> Signed-off-by: Xu Yilun
>
platform device as well as
> the MAX10 BMC spi slave info. A spi-altera driver will be matched to
> handle following the SPI work.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Russ Weight
> Reviewed-by: Tom Rix
port) will create DFL devices on
> enumeration. DFL drivers could be registered on this bus to match these
> DFL devices. They are matched by dfl type & feature_id.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Russ Weight
> -Original Message-
> From: linux-fpga-ow...@vger.kernel.org
> On Behalf Of Xu Yilun
> Sent: Monday, August 10, 2020 10:41 AM
> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun
> > > +static int dfl_bus_uevent(struct device *dev, struct kobj_uevent_env
> *env)
> > > +{
> > > +struct dfl_device *ddev = to_dfl_dev(dev);
> > > +
> > > +return add_uevent_var(env, "MODALIAS=dfl:t%08Xf%04X",
> > > + ddev->type, ddev->feature_id);
> >
> > Then we only print 12bit of feature
ndled by separate driver modules.
>
> DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on
> enumeration. DFL drivers could be registered on this bus to match these
> DFL devices. They are matched by dfl type & feature_id.
>
> Signed-off-by: Xu Yilun
>
e of FIU headers are still mapped in dfl
> bus driver. The FIU headers have some fundamental functions (sriov set,
> port enable/disable) needed for dfl bus devices and other sub features.
> They should not be unmapped as long as dfl bus device is alive.
>
> Signed-off-by: Xu Yilun
> Reviewed-by: Tom Rix
Acked-by: Wu Hao
Thanks
Hao
> Subject: Re: [PATCH v3 4/4] fpga: dfl: add support for N3000 nios private
> feature
>
> Thanks for your quick response, I'm OK with most changes. Some comments
> inline.
>
> On Tue, Aug 04, 2020 at 08:56:12PM +0800, Wu, Hao wrote:
> > > Subject: [PATCH v3 4/
> +++ b/MAINTAINERS
> > @@ -6805,6 +6805,7 @@ F:drivers/net/ethernet/nvidia/*
> >
> > FPGA DFL DRIVERS
> > M: Wu Hao
> > +R: Tom Rix
> > L: linux-f...@vger.kernel.org
> > S: Maintained
> > F: Documentation/fpga/dfl.rst
>
well as
> the MAX10 BMC spi slave info. A spi-altera driver will be matched to
> handle following the SPI work.
>
> Signed-off-by: Xu Yilun
> Signed-off-by: Wu Hao
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Russ Weight
> Reviewed-by: Tom Rix
> ---
&g
> > > +}
> > > +
> > > +dfl_dev->type = feature_dev_id_type(pdev);
> > > +dfl_dev->feature_id = (unsigned long long)feature->id;
> > > +
> > > +dfl_dev->dev.parent = &pdev->dev;
> > > +dfl_dev->dev.bus = &dfl_bus_type;
> > > +dfl_dev->dev.release = release_dfl_dev;
> > > +dev_set_name(&dfl_dev
> On 7/16/20 8:48 PM, Wu, Hao wrote:
> >> Subject: Re: [PATCH 0/2] Modularization of DFL private feature drivers
> >>
> >> Generally i think this is a good approach.
> >>
> >> However I do have concern.
> >>
> >> The feature_i
e of FIU headers are still mapped in dfl
> bus driver. The FIU headers have some fundamental functions (sriov set,
> port enable/disable) needed for dfl bus devices and other sub features.
> They should not be unmapped as long as dfl bus device is alive.
>
> Signed-off-by: Xu Yilun
>
> -Original Message-
> From: Xu, Yilun
> Sent: Wednesday, July 15, 2020 1:38 PM
> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun ;
> Wu, Hao ; Matthew Gerlach
> ; Weight, Russel
> -Original Message-
> From: linux-fpga-ow...@vger.kernel.org
> On Behalf Of Xu Yilun
> Sent: Wednesday, July 15, 2020 1:38 PM
> To: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun
> Subject: Re: [PATCH 0/2] Modularization of DFL private feature drivers
>
> Generally i think this is a good approach.
>
> However I do have concern.
>
> The feature_id in dfl is magic number, similar to pci id but without a vendor
> id.
>
> Is it possible to add something like a vendor id so
> On Thu, Jul 09, 2020 at 06:00:40AM -0700, Tom Rix wrote:
> >
> > On 7/9/20 3:14 AM, Wu, Hao wrote:
> > >> On Thu, Jul 09, 2020 at 05:10:49PM +0800, Wu, Hao wrote:
> > >>>> Subject: [PATCH] fpga: dfl: pci: add device id for Intel FPGA PAC N3000
> &
> On Thu, Jul 09, 2020 at 05:10:49PM +0800, Wu, Hao wrote:
> > > Subject: [PATCH] fpga: dfl: pci: add device id for Intel FPGA PAC N3000
> > >
> > > Add PCIe Device ID for Intel FPGA PAC N3000.
> > >
> > > Signed-off-by: Wu Hao
> > > Sign
> Subject: [PATCH] fpga: dfl: pci: add device id for Intel FPGA PAC N3000
>
> Add PCIe Device ID for Intel FPGA PAC N3000.
>
> Signed-off-by: Wu Hao
> Signed-off-by: Xu Yilun
> Signed-off-by: Matthew Gerlach
> Signed-off-by: Russ Weight
> ---
> drivers/f
> On 6/28/20 8:12 PM, Wu, Hao wrote:
> >> -Original Message-
> >> From: linux-fpga-ow...@vger.kernel.org ow...@vger.kernel.org>
> >> On Behalf Of Xu Yilun
> >> Sent: Monday, June 29, 2020 10:19 AM
> >> To: t...@redhat.com
> >
> -Original Message-
> From: linux-fpga-ow...@vger.kernel.org
> On Behalf Of Xu Yilun
> Sent: Monday, June 29, 2020 10:19 AM
> To: t...@redhat.com
> Cc: m...@kernel.org; linux-f...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Wu, Hao ;
> matthew.gerl...@linux
> -Original Message-
> From: linux-fpga-ow...@vger.kernel.org
> On Behalf Of t...@redhat.com
> Sent: Sunday, June 7, 2020 5:03 AM
> To: m...@kernel.org
> Cc: linux-f...@vger.kernel.org; linux-kernel@vger.kernel.org; Tom Rix
>
> Subject: [PATCH 1/1] fpga: dfl: Fix dead store
>
Thanks for
> -Original Message-
> From: John Hubbard
> Sent: Tuesday, May 26, 2020 6:18 AM
> To: LKML
> Cc: John Hubbard ; Xu, Yilun ;
> Wu, Hao ; Moritz Fischer ; linux-
> f...@vger.kernel.org
> Subject: [PATCH v3] fpga: dfl: afu: convert get_user_pages() -->
> pin_u
> >> Hi Moritz and FPGA developers,
> >>
> >> Is this OK? And if so, is it going into your git tree? Or should I
> >> send it up through a different tree? (I'm new to the FPGA development
> >> model).
> >
> > I can take it, sorry for sluggish response.
> >
>
> That's great news, thanks Moritz! Sor
> -Original Message-
> From: Xu, Yilun
> Sent: Thursday, May 14, 2020 10:30 AM
> To: Souptick Joarder
> Cc: Wu, Hao ; m...@kernel.org; linux-
> f...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] fpga: dfl: afu: Corrected error handling levels
I think Moritz had already applied it to his tree per last submission.
https://lkml.org/lkml/2020/3/21/373
Thanks
Hao
> -Original Message-
> From: matthew.gerl...@linux.intel.com
> Sent: Saturday, May 9, 2020 2:21 AM
> To: Gustavo A. R. Silva
> Cc: Wu, Hao ; linux-f...@
On Mon, Aug 05, 2019 at 05:52:40PM +0200, Greg KH wrote:
> On Sun, Aug 04, 2019 at 06:20:16PM +0800, Wu Hao wrote:
> > As these two functions are used by other private features. e.g.
> > in error reporting private feature, it requires to check port status
> > and reset po
On Thu, Aug 01, 2019 at 04:53:39PM -0500, Bjorn Helgaas wrote:
> [+cc FPGA folks, just FYI; I'm pretty sure PCI could do a much better
> job supporting FPGAs, so any input is welcome!]
>
> On Wed, Jul 03, 2019 at 06:03:41PM +0300, Mika Westerberg wrote:
> > On Wed, Jul 03, 2019 at 08:39:53AM -0500
On Wed, Jul 24, 2019 at 11:37:44AM +0200, Greg KH wrote:
> On Tue, Jul 23, 2019 at 12:51:26PM +0800, Wu Hao wrote:
> > This patch enables the standard sriov support. It allows user to
> > enable SRIOV (and VFs), then user could pass through accelerators
> > (VFs) into virtu
On Wed, Jul 10, 2019 at 07:54:17AM +0200, Greg KH wrote:
> On Wed, Jul 10, 2019 at 01:07:46PM +0800, Wu Hao wrote:
> > On Fri, Jul 05, 2019 at 08:23:47AM +0800, Wu Hao wrote:
> > > Hi Greg / Moritz
> > >
> > > This is v2 patchset which adds more features to F
On Fri, Jul 05, 2019 at 08:23:47AM +0800, Wu Hao wrote:
> Hi Greg / Moritz
>
> This is v2 patchset which adds more features to FPGA DFL. This patchset
> is made on top of patch[1] and char-misc-next tree. Documentation patch
> for DFL is dropped from this patchset, and will resub
As these two functions are used by other private features. e.g.
in error reporting private feature, it requires to check port status
and reset port for error clearing.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
STP (SignalTap) is one of the private features under the port for
debugging. This patch adds private feature driver support for it
to allow userspace applications to mmap related mmio region and
provide STP service.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked
/MODULE_VERSION modifications. (patch #1, #3, #4, #6)
- remove argsz from new ioctls. (patch #2)
- replace sysfs_create/remove_* with device_add/remove_* for sysfs entries.
(patch #5, #8, #11)
[1] [PATCH] fpga: dfl: use driver core functions, not sysfs ones.
https://lkml.org/lkml/2019/7/4/36
Wu Hao
in integrated
solution that AVX512 is always supported. This revision 2
hardware doesn't support 32bit PR.
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2: remove DRV/MODULE_VERSION modifications
---
dr
userspace interfaces on PF.
Signed-off-by: Zhang Yi Z
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Moritz Fischer
---
v2: remove argsz from ioctls.
---
drivers/fpga/dfl-fme-main.c | 30
drivers/fpga/dfl.c| 107
Error reporting is one important private feature, it reports error
detected on port and accelerated function unit (AFU). It introduces
several sysfs interfaces to allow userspace to check and clear
errors detected by hardware.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
This patch enables the standard sriov support. It allows user to
enable SRIOV (and VFs), then user could pass through accelerators
(VFs) into virtual machine or use VFs directly in host.
Signed-off-by: Zhang Yi Z
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2: switch to device_add/remove_groups for sysfs.
---
Documentation/ABI/testing/sysfs-platform-dfl-fme | 75 +
drivers/fpga/Makefile| 2 +-
drivers/fpga/dfl-fme
d-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2: rebased, and remove DRV/MODULE_VERSION modifications
---
Documentation/ABI/testing/sysfs-platform-dfl-port | 30 +
drivers/fpga/dfl-afu-m
This patch adds id_table for each dfl private feature driver,
it allows to reuse same private feature driver to match and support
multiple dfl private features.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2
interface
is exposed to userspace application for this purpose too.
Signed-off-by: Ananda Ravuri
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2: rebased, and switched to use device_add/remove_groups for sysfs
This patch adds 3 read-only sysfs interfaces for FPGA Management Engine
(FME) block for capabilities including cache_size, fabric_version and
socket_id.
Signed-off-by: Luwei Kang
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v2: rebased
ce_remove_groups()
Hi Greg,
Thanks for this patch. It looks good, and works well in my side.
I will follow the same (replace sysfs_create/remove_* with
device_add/remove_group) to rework my patchset too. Thanks.
Hao
>
> Cc: Wu Hao
> Cc: Alan Tull
> Cc: Moritz Fischer
> Cc: li
On Fri, Jun 28, 2019 at 10:13:33AM +0800, Wu Hao wrote:
> On Thu, Jun 27, 2019 at 06:12:56PM -0700, Moritz Fischer wrote:
> > Hi Wu,
> >
> > On Thu, Jun 27, 2019 at 12:44:45PM +0800, Wu Hao wrote:
> > > This patch adds virtualization support description for DFL base
This patch adds virtualization support description for DFL based
FPGA devices (based on PCIe SRIOV), and introductions to new
interfaces added by new dfl private feature drivers.
[m...@kernel.org: Fixed up to make it work with new reStructuredText docs]
Signed-off-by: Xu Yilun
Signed-off-by: Wu
On Fri, Jun 28, 2019 at 10:55:14AM -0700, Guenter Roeck wrote:
> On Thu, Jun 27, 2019 at 12:53:38PM +0800, Wu Hao wrote:
> > This patch adds support for power management private feature under
> > FPGA Management Engine (FME). This private feature driver registers
> &
On Thu, Jun 27, 2019 at 06:12:56PM -0700, Moritz Fischer wrote:
> Hi Wu,
>
> On Thu, Jun 27, 2019 at 12:44:45PM +0800, Wu Hao wrote:
> > This patch adds virtualization support description for DFL based
> > FPGA devices (based on PCIe SRIOV), and introductions to new
> &
On Fri, Jun 28, 2019 at 12:53:29AM +0800, Greg KH wrote:
> On Thu, Jun 27, 2019 at 01:09:55PM +0800, Wu Hao wrote:
> > This patch adds support for performance reporting private feature
> > for FPGA Management Engine (FME). Now it supports several different
> > performanc
ee example below:
perf stat -e fme0/fab_mmio_read/,fme0/fab_port_mmio_write,portid=0/
Performance counter stats for 'system wide':
0 fme0/fab_mmio_read/
fme0/fab_port_mmio_write,portid=0/
2.141064085 seconds time elapsed
Signed-off-by: Luwei Kang
From: Xu Yilun
This patch adds description for performance reporting support for
Device Feature List (DFL) based FPGA.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/fpga/dfl.txt | 83 ++
1 file changed, 83 insertions(+)
diff
)
[1]https://lkml.org/lkml/2019/5/27/11
[2]https://lkml.org/lkml/2019/5/27/18
[3]https://lkml.org/lkml/2019/6/27/29
[4]https://lkml.org/lkml/2019/6/27/49
Wu Hao (1):
fpga: dfl: fme: add performance reporting support
Xu Yilun (1):
Documentation: fpga: dfl: add description for performance reporting
This patch adds virtualization support description for DFL based
FPGA devices (based on PCIe SRIOV), and introductions to new
interfaces added by new dfl private feature drivers.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
---
Documentation/fpga/dfl.txt | 101
STP (SignalTap) is one of the private features under the port for
debugging. This patch adds private feature driver support for it
to allow userspace applications to mmap related mmio region and
provide STP service.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked
d-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
---
v3: replace scnprintf with sprintf in sysfs interfaces.
update sysfs doc kernel version and date.
v4: update sysfs doc date.
---
Documentation/ABI/testing/sysfs-platform-dfl-port | 30 +
dr
This patch adds id_table for each dfl private feature driver,
it allows to reuse same private feature driver to match and support
multiple dfl private features.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/dfl-afu-main.c | 14
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