> > The limitation is not on the MAC, PCS or the PHY. For Intel mgbe, the
> > overclocking of 2.5 times clock rate to support 2.5G is only able to
> > be configured in the BIOS during boot time. Kernel driver has no
> > access to modify the clock rate for 1Gbps/2.5G mode. The way to
> > determined
> > > You have a MAC and an PCS in the stmmac IP block. That then has some
> > > sort of SERDES interface, running 1000BaseX, SGMII, SGMII
> > > overclocked at 2.5G or 25000BaseX. Connected to the SERDES you have
> > > a PHY which converts to copper, giving you 2500BaseT.
> > >
> > > You said earli
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
-change subject from "net: intel" to "stmmac: intel"
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 +
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 +
2 files changed, 11 insertions(+)
diff
> On Fri, Apr 02, 2021 at 07:45:04AM +0000, Voon, Weifeng wrote:
> > > > + /* 2.5G mode only support 2500baseT full duplex only */
> > > > + if (priv->plat->has_gmac4 && priv->plat->speed_2500_en) {
> > > >
> > + /* 2.5G mode only support 2500baseT full duplex only */
> > + if (priv->plat->has_gmac4 && priv->plat->speed_2500_en) {
> > + phylink_set(mac_supported, 2500baseT_Full);
> > + phylink_set(mask, 10baseT_Half);
> > + phylink_set(mask, 10baseT_Full);
> > +
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
- Refactor out a huge if statement into separate subfunctions.
- Removed the netdev_info for every successful request of IRQs.
- Return 0 for each successful request of IRQs.
---
drivers/net/ethernet/stmicro/stmma
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
- Moved the msi tx/rx base vector check before alloc irq
- Restuctu
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
Changes:
v1 -> v2
-Remove defensive check for invalid dev poin
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
> On Tue, 16 Mar 2021 20:18:21 +0800 Voon Weifeng wrote:
> > From: Ong Boon Leong
> >
> > Now we introduce MSI interrupt service routines and hook these
> > routines up if stmmac_open() sees valid irq line being requested:-
> >
> > stmmac_mac_interrupt()
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +-
1 file changed
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 15 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 415 --
include/linux/stmmac.h| 8 +
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 +++
1
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
From: Ong Boon Leong
In preparation to make stmmac support multi-vector MSI, we introduce the
interrupt status masking according to RX, TX or RXTX. Default to use RXTX
inside stmmac_dma_interrupt(), so there is no run-time logic difference
now.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon
From: Ong Boon Leong
Refactor stmmac_interrupt() by introducing stmmac_common_interrupt()
so that we prepare the ISR operation to be friendly to MSI later.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 +++
1
This patchset adds support for multi MSI interrupts in addition to
current single common interrupt implementation. Each MSI interrupt is tied
to a newly introduce interrupt service routine(ISR). Hence, each interrupt
will only go through the corresponding ISR.
In order to increase the efficiency,
-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.
Signed-off-by: Ong Boon Leong
Co-developed-by: Voon Weifeng
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +-
1 file changed
ned-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 15 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 415 --
include/linux/stmmac.h| 8 +
ch TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.
Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.
Signed-off-by: Wong, Vee Khee
Co-developed-by: Voon Weife
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v3 changelog:
-Changed stmmac_lpi_entry_timer_config() to static function
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not require
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v3 changelog:
-Changed stmmac_lpi_entry_timer_config() to static function
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not require
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
v2 changelog:
-removed #define for LPI_ET_ENABLE and LPI_ET_DISABLE and directly use
literals
-removed not required function header in stmmac.h
-renamed stmmac_lpi_entry_timer_e
alue is configured through ethtool. The driver will auto
> select the LPI HW timer if the value in the HW timer supported range.
> Else, the driver will fallback to SW timer.
>
> Signed-off-by: Vineetha G. Jaya Kumaran
> Signed-off-by: Voon Weifeng
Please help to review and comment. Thanks.
Weifeng
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 ++
drivers/ne
imer supported range.
> Else, the driver will fallback to SW timer.
>
> Signed-off-by: Vineetha G. Jaya Kumaran
> Signed-off-by: Voon Weifeng
> ---
Please drop this patch. Sorry for accidentally sending out this patch.
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 +++
drivers/ne
the driver will fallback to SW timer.
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 2 ++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 24 ++
drivers/ne
"stmmac: add the Energy Efficient Ethernet support")
Signed-off-by: Vineetha G. Jaya Kumaran
Signed-off-by: Voon Weifeng
Changelog V2
*Not removing/modifying the eee_timer.
*EEE LPI timer can be configured through ethtool and also the eee_timer
module param.
*EEE TW Timer will be configure
h is not correct.
Hence, this patch fixes the the configuration of LPI TW timer via
module parameters instead of ethtool. And, "ethtool --set-eee tx-timer"
should configure EEE LPI timer.
Fixes: d765955d2ae0 ("stmmac: add the Energy Efficient Ethernet support")
Signed-off-by: Vin
From: Rusaimi Amira Ruslan
Adding reference clock (1us tic) for all LPI timer on Intel platforms.
The reference clock is derived from ptp clk. This also enables all LPI
counter.
Signed-off-by: Rusaimi Amira Ruslan
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/dwmac
e58ad6 ("net: stmmac: Fix a race in EEE enable callback")
Signed-off-by: Voon Weifeng
---
.../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
b/drive
e() will sleep until wake_up() is
called by the interrupt handler.
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh, Hock Leong
Reviewed-by: Ong Boon Leong
Signed-off-by: Chuah, Kim Tatt
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
Changelog v3
*Move the changelog to before the -
> > The change log is near the end of the patch:
> > /**
> > --
> > Changelog v2
> > *mdio interrupt mode or polling mode will depends on mdio interrupt
> > enable bit *Disable the mdio interrupt enable bit in stmmac_release
> > *Remove the condition for initialize wait queues *Applied reverse
> >
> On Wed, Sep 04, 2019 at 10:02:54PM +0800, Voon Weifeng wrote:
> > From: "Chuah, Kim Tatt"
> >
> > DW EQoS v5.xx controllers added capability for interrupt generation
> > when MDIO interface is done (GMII Busy bit is cleared).
> > This patch adds su
e() will sleep until wake_up() is
called by the interrupt handler.
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh, Hock Leong
Reviewed-by: Ong Boon Leong
Signed-off-by: Chuah, Kim Tatt
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
diff --git a/drivers/net/ethernet/stmicro/stmmac/commo
> On 8/28/19 8:41 AM, Ong, Boon Leong wrote:
> >> On Tue, Aug 27, 2019 at 03:23:34PM +, Voon, Weifeng wrote:
> >>>>>> Make mdiobus_scan() to try harder to look for any PHY that only
> >>>> talks C45.
> >>>>> If you are not usin
> >> DW EQoS v5.xx controllers added capability for interrupt generation
> >> when MDIO interface is done (GMII Busy bit is cleared).
> >> This patch adds support for this interrupt on supported HW to avoid
> >> polling on GMII Busy bit.
> >>
> >> stmmac_mdio_read() & stmmac_mdio_write() will sleep
> > > Make mdiobus_scan() to try harder to look for any PHY that only
> talks C45.
> > If you are not using Device Tree or ACPI, and you are letting the MDIO
> > bus be scanned, it sounds like there should be a way for you to
> > provide a hint as to which addresses should be scanned (that's
> > mi
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -174,6 +175,19 @@ static int intel_mgbe_common_data(struct
> pci_dev *pdev,
> > > plat->axi->axi_blen[1] = 8;
> > > plat->axi->axi_blen[2] = 16;
> > >
> > > + plat->ptp_max_adj = plat->clk_ptp_rate;
> > > +
> > > + /* Set system
> There is something wrong with the clock on the computer you are posting
> these patches from, the date in these postings are in the future by
> several hours.
>
> This messes up the ordering of changes in patchwork and makes my life
> miserable to a certain degree, so please fix this.
>
> Thank
From: Ong Boon Leong
Make mdiobus_scan() to try harder to look for any PHY that only talks C45.
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index bd04fe762056..30dbc48b4c7e 100644
--- a/drivers/net/phy
e() will sleep until wake_up() is
called by the interrupt handler.
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh, Hock Leong
Reviewed-by: Ong Boon Leong
Signed-off-by: Chuah, Kim Tatt
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
diff --git a/drivers/net/ethernet/stmicro/stmmac/commo
Added TGL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
Signed-off-by: Ong Boon Leong
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 29
1 file changed, 29 insertions(+)
diff --git a/drivers/net/ethernet
Added EHL RGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
Signed-off-by: Ong Boon Leong
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk,
ptp clock and ptp_max_adj to 200MHz.
Signed-off-by: Voon Weifeng
Signed-off-by: Ong Boon Leong
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 21 +
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3
tgl, ehl. The third layer will be configuration
that tied to the PCI ID only based on speed and RGMII/SGMII interface.
EHL and TGL will also having a higher system clock which is 200Mhz.
Voon Weifeng (4):
net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID
net: stmmac: add TGL SGMII 1Gbps PCI
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
Signed-off-by: Ong Boon Leong
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 107 +++
1 file changed, 107 insertions(+)
diff --git a/drivers/net/ethernet
Leong
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 18cadf0b0d66..4304c1abc5d1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net
> > If the community prefers readability
>
> Readability nearly always comes first. There is nothing performance
> critical here, MDIO is a slow bus. So the code should be readable,
> simple to understand.
>
Noted and thanks for the comments.
>
> , I will suggest to do the c45 setup in
> > both
> I think there is too much passing variables around by reference than by
> value, to make this code easy to understand.
>
> Maybe a better structure would be
>
> static int stmmac_mdion_c45_read(struct stmmac_priv *priv, int phyaddr,
> int phyreg) {
>
> unsigned int reg_shift = priv->hw->
> > > > > > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct
> > > > > > mii_bus *bus,
> > > > > int phyaddr, int phyreg)
> > > > > > struct stmmac_priv *priv = netdev_priv(ndev);
> > > > > > unsigned int mii_address = priv->hw->mii.addr;
> > > > > > unsigned int mii_data = priv
> > > > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct mii_bus
> > > > *bus,
> > > int phyaddr, int phyreg)
> > > > struct stmmac_priv *priv = netdev_priv(ndev);
> > > > unsigned int mii_address = priv->hw->mii.addr;
> > > > unsigned int mii_data = priv->hw->mii.da
> > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct mii_bus *bus,
> int phyaddr, int phyreg)
> > struct stmmac_priv *priv = netdev_priv(ndev);
> > unsigned int mii_address = priv->hw->mii.addr;
> > unsigned int mii_data = priv->hw->mii.data;
> > - u32 v;
> > - int data;
> >
From: Weifeng Voon
Enable GMAC v4.xx and beyond to support 16KiB buffer.
Signed-off-by: Weifeng Voon
Signed-off-by: Ong Boon Leong
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index cf6436d3d6c7..dbde23e7e169 100644
---
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
> Hi all,
>
> In commit
>
> d0bb82fd6018 ("net: stmmac: set IC bit when transmitting frames with
> HW timestamp")
>
> Fixes tag
>
> Fixes: f748be531d70 ("net: stmmac: Rework coalesce timer and fix
> multi-queue races")
>
> has these problem(s):
>
> - Subject does not match target commit
> > +static int est_poll_srwo(void *ioaddr) {
> > + /* Poll until the EST GCL Control[SRWO] bit clears.
> > +* Total wait = 12 x 50ms ~= 0.6s.
> > +*/
> > + unsigned int retries = 12;
> > + unsigned int value;
> > +
> > + do {
> > + value = TSN_RD32(ioaddr + MTL_EST_GCL_CT
races")
Signed-off-by: Roland Hii
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 06dd51f47cfd..06358fe5b245 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stm
= 0xFFFD
Previously, the 0x1 is mistakenly written as 1.
This is further simplified from
sec = (0x1ULL - sec);
to
sec = -sec;
Fixes: ba1ffd74df74 ("stmmac: fix PTP support for GMAC4")
Signed-off-by: Roland Hii
Signed-off-by: Ong Boon Leong
Signed-of
TSN HW tunable data for PTP Time Offset Value(PTOV),
Current Time Offset Value(CTOV) and Time Interval Shift
Amount(TILS) are added as platform data. These platform
data are set after tsn setup.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 16
aprio \
num_tc 3 \
map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 \
queues 1@0 1@1 2@2 \
base-time 1000 \
sched-entry S 03 30 \
sched-entry S 02 30 \
sched-entry S 06 40 \
clockid CLOCK_TAI
offload 1
Signed-off-by: Voon Weifeng
---
driver
Gate Control configuration either from driver data store or
hardware.
We extend the main driver logic to include basic TSN capability discovery,
and setup. We also add EST feature enable/disable control.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Signed
IEEE 802.1Qbv configuration functionalities
Vinicius Costa Gomes (1):
taprio: Add support for hardware offloading
Voon Weifeng (3):
net: stmmac: gcl errors reporting and its interrupt handling
net: stmmac: enable HW offloading for tc taprio
net: stmmac: Set TSN HW tunable after tsn setup
also added functionality to get and clear the gcl errors.
The ISR handling takes place when EST feature is enabled by user.
Signed-off-by: Voon Weifeng
Signed-off-by: Ong Boon Leong
---
drivers/net/ethernet/stmicro/stmmac/common.h | 4 +
drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
, each bit
in gate_mask references a transmission queue: bit 0 for queue 0, bit 1
for queue 1, and so on. This is done so the driver doesn't need to
know about traffic classes.
Signed-off-by: Vinicius Costa Gomes
Signed-off-by: Voon Weifeng
---
include/linux/netdevice.h | 1 +
includ
From: Ong Boon Leong
We introduce support for driver that has v5.10 IP and is also using
xPCS as MMD. This can be easily enabled for other product that integrates
xPCS that is not using v5.00 IP.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b
t platform-specific C37 AN PCS mode selection for MII MMD,
we introduce 'pcs_mode' in platform data.
The basic framework for xPCS interrupt handling is implemented too.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by: Baoli Zhang
Signed-of
: stmmac: add xPCS functions for device with DWMACv5.1
Voon Weifeng (1):
net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
and Link
Partner ability are implemented. The implementation supports the C37
AN for 1000BASE-X and SGMII (MAC side SGMII only).
Tested-by: Tan, Tee Min
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/s
> > This patch-set is to enable Ethernet controller (DW Ethernet QoS and
> > DW Ethernet PCS) with SGMII interface in Elkhart Lake.
> > The DW Ethernet PCS is the Physical Coding Sublayer that is between
> > Ethernet MAC and PHY and uses MDIO Clause-45 as Communication.
>
> This series look fine t
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b
t platform-specific C37 AN PCS mode selection for MII MMD,
we introduce 'pcs_mode' in platform data.
The basic framework for xPCS interrupt handling is implemented too.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by: Baoli Zhang
Signed-of
From: Ong Boon Leong
We introduce support for driver that has v5.10 IP and is also using
xPCS as MMD. This can be easily enabled for other product that integrates
xPCS that is not using v5.00 IP.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by
clause 45 mdio support
Ong Boon Leong (3):
net: stmmac: introducing support for DWC xPCS logics
net: stmmac: add xpcs function hooks into main driver and ethtool
net: stmmac: add xPCS functions for device with DWMACv5.1
Voon Weifeng (1):
net: stmmac: add EHL SGMII 1Gbps PCI info and PCI
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
and Link
Partner ability are implemented. The implementation supports the C37
AN for 1000BASE-X and SGMII (MAC side SGMII only).
Tested-by: Tan, Tee Min
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/s
> > > Did you rebase this series against latest net-next tree ?
> > >
> > > Because you are missing MMC module in your HWIF table entry. This
> > > module was recently added with the addition of selftests.
> >
> > No, the base is on last Thursday. Let me rebased on the latest net-next and
> submit
>
> > + plat->axi->axi_lpi_en = 0;
> > + plat->axi->axi_xit_frm = 0;
> > + plat->axi->axi_wr_osr_lmt = 0;
>
> This is not a valid value.
Can you please explained why is not a valid value? And what should
be the recommended value?
Databook mentioned that "Maximum outstanding requests =
WR_
> > +static void stmmac_mdio_c45_setup(struct stmmac_priv *priv, int phyreg,
> > + u32 *val, u32 *data)
> > +{
> > + unsigned int reg_shift = priv->hw->mii.reg_shift;
> > + unsigned int reg_mask = priv->hw->mii.reg_mask;
>
> Reverse christmas tree here. You also sho
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b
clause 45 mdio support
Ong Boon Leong (3):
net: stmmac: introducing support for DWC xPCS logics
net: stmmac: add xpcs function hooks into main driver and ethtool
net: stmmac: add xPCS functions for device with DWMACv5.1
Voon Weifeng (1):
net: stmmac: add EHL SGMII 1Gbps PCI info and PCI
From: Ong Boon Leong
We introduce support for driver that has v5.10 IP and is also using
xPCS as MMD. This can be easily enabled for other product that integrates
xPCS that is not using v5.00 IP.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by
t platform-specific C37 AN PCS mode selection for MII MMD,
we introduce 'pcs_mode' in platform data.
The basic framework for xPCS interrupt handling is implemented too.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by: Baoli Zhang
Signed-of
and Link
Partner ability are implemented. The implementation supports the C37
AN for 1000BASE-X and SGMII (MAC side SGMII only).
Tested-by: Tan, Tee Min
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/s
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
>
> Did you rebase this series against latest net-next tree ?
>
> Because you are missing MMC module in your HWIF table entry. This module
> was recently added with the addition of selftests.
No, the base is on last Thursday. Let me rebased on the latest net-next and
submit for v4.
Thanks,
Wei
clause 45 mdio support
Ong Boon Leong (3):
net: stmmac: introducing support for DWC xPCS logics
net: stmmac: add xpcs function hooks into main driver and ethtool
net: stmmac: add xPCS functions for device with DWMACv5.1
Voon Weifeng (1):
net: stmmac: add EHL SGMII 1Gbps PCI info and PCI
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b
and Link
Partner ability are implemented. The implementation supports the C37
AN for 1000BASE-X and SGMII (MAC side SGMII only).
Tested-by: Tan, Tee Min
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Signed-off-by: Ong Boon Leong
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/s
From: Ong Boon Leong
We introduce support for driver that has v5.10 IP and is also using
xPCS as MMD. This can be easily enabled for other product that integrates
xPCS that is not using v5.00 IP.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by
t platform-specific C37 AN PCS mode selection for MII MMD,
we introduce 'pcs_mode' in platform data.
The basic framework for xPCS interrupt handling is implemented too.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by: Baoli Zhang
Signed-of
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
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