On 4/14/2021 11:45 PM, Greg KH wrote:
On Wed, Apr 14, 2021 at 10:49:41AM -0400, Tianyu Lan wrote:
From: Tianyu Lan
UIO HV driver should not load in the isolation VM for security reason.
Return ENOTSUPP in the hv_uio_probe() in the isolation VM.
Signed-off-by: Tianyu Lan
---
drivers/uio
Hi Stephen:
Thanks for your review.
On 4/15/2021 12:17 AM, Stephen Hemminger wrote:
On Wed, 14 Apr 2021 17:45:51 +0200
Greg KH wrote:
On Wed, Apr 14, 2021 at 10:49:41AM -0400, Tianyu Lan wrote:
From: Tianyu Lan
UIO HV driver should not load in the isolation VM for security reason
On 4/14/2021 11:50 PM, Christoph Hellwig wrote:
+struct dma_range {
+ dma_addr_t dma;
+ u32 mapping_size;
+};
That's a rather generic name that is bound to create a conflict sooner
or later.
Good point. Will update.
#include "hyperv_net.h"
#include "netvsc_trace.h"
+#in
On 4/14/2021 11:41 PM, Christoph Hellwig wrote:
+EXPORT_SYMBOL_GPL(hv_ghcb_msr_write);
Just curious, who is going to use all these exports? These seems like
extremely low-level functionality. Isn't there a way to build a more
useful higher level API?
Yes, will remove it.
Hi Christoph:
Thanks for your review.
On 4/14/2021 11:40 PM, Christoph Hellwig wrote:
+/*
+ * hv_set_mem_host_visibility - Set host visibility for specified memory.
+ */
I don't think this comment really clarifies anything over the function
name. What is 'host visibility'
OK. Will u
Hi Greg:
Thanks for your review.
On 4/14/2021 12:00 AM, Greg KH wrote:
On Tue, Apr 13, 2021 at 11:22:13AM -0400, Tianyu Lan wrote:
From: Tianyu Lan
UIO HV driver should not load in the isolation VM for security reason.
Why? I need a lot more excuse than that.
The reason is that
From: Tianyu Lan
In Isolation VM, all shared memory with host needs to mark visible
to host via hvcall. vmbus_establish_gpadl() has already done it for
netvsc rx/tx ring buffer. The page buffer used by vmbus_sendpacket_
mpb_desc() still need to handle. Use DMA API to map/umap these
memory during
From: Tianyu Lan
In Isolation VM, all shared memory with host needs to mark visible
to host via hvcall. vmbus_establish_gpadl() has already done it for
netvsc rx/tx ring buffer. The page buffer used by vmbus_sendpacket_
pagebuffer() still need to handle. Use DMA API to map/umap these
memory
From: Tianyu Lan
Hyper-V Isolation VM requires bounce buffer support. To use swiotlb
bounce buffer, add Hyper-V dma ops and use swiotlb functions in the
map and unmap callback.
Allocate bounce buffer in the Hyper-V code because bounce buffer
needs to be accessed via extra address space(e.g
From: Tianyu Lan
For Hyper-V isolation VM with AMD SEV SNP, the bounce buffer(shared memory)
needs to be accessed via extra address space(e.g address above bit39).
Hyper-V code may remap extra address space outside of swiotlb. swiotlb_bounce()
needs to use remap virtual address to copy data from
From: Tianyu Lan
UIO HV driver should not load in the isolation VM for security reason.
Return ENOTSUPP in the hv_uio_probe() in the isolation VM.
Signed-off-by: Tianyu Lan
---
drivers/uio/uio_hv_generic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/uio/uio_hv_generic.c b
From: Tianyu Lan
VMbus ring buffer are shared with host and it's need to
be accessed via extra address space of Isolation VM with
SNP support. This patch is to map the ring buffer
address in extra address space via ioremap(). HV host
visibility hvcall smears data in the ring buffer and
so
From: Tianyu Lan
The physical address of monitor pages in the CHANNELMSG_INITIATE_CONTACT
msg should be in the extra address space for SNP support and these
pages also should be accessed via the extra address space inside Linux
guest and remap the extra address by ioremap function.
Signed-off
From: Tianyu Lan
Hyper-V provides ghcb hvcall to handle VMBus
HVCALL_SIGNAL_EVENT and HVCALL_POST_MESSAGE
msg in SNP Isolation VM. Add such support.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/ivm.c | 69 +
arch/x86/include/asm/mshyperv.h | 1
From: Tianyu Lan
Hyper-V provides GHCB protocol to write Synthetic Interrupt
Controller MSR registers and these registers are emulated by
Hypervisor rather than paravisor.
Hyper-V requests to write SINTx MSR registers twice(once via
GHCB and once via wrmsr instruction including the proxy bit 21
From: Tianyu Lan
"Resend all patches because someone in CC list didn't receive all
patchset. Sorry for nosy."
Hyper-V provides two kinds of Isolation VMs. VBS(Virtualization-based
security) and AMD SEV-SNP unenlightened Isolation VMs. This patchset
is to add support for the
From: Tianyu Lan
Add new hvcall guest address host visibility support. Mark vmbus
ring buffer visible to host when create gpadl buffer and mark back
to not visible when tear down gpadl buffer.
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/Makefile
From: Tianyu Lan
Hyper-V exposes GHCB page via SEV ES GHCB MSR for SNP guest
to communicate with hypervisor. Map GHCB page for all
cpus to read/write MSR register and submit hvcall request
via GHCB.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/hv_init.c | 52
From: Tianyu Lan
Hyper-V exposes shared memory boundary via cpuid HYPERV_
CPUID_ISOLATION_CONFIG and store it in the shared_gpa_
boundary of ms_hyperv struct. This prepares to share
memory with host for AMD SEV SNP guest.
Signed-off-by: Tianyu Lan
---
arch/x86/kernel/cpu/mshyperv.c | 2
On 4/14/2021 2:43 PM, Christoph Hellwig wrote:
On Tue, Apr 13, 2021 at 11:22:14AM -0400, Tianyu Lan wrote:
From: Tianyu Lan
For Hyper-V isolation VM with AMD SEV SNP, the bounce buffer(shared memory)
needs to be accessed via extra address space(e.g address above bit39).
Hyper-V code may remap
From: Tianyu Lan
For Hyper-V isolation VM with AMD SEV SNP, the bounce buffer(shared memory)
needs to be accessed via extra address space(e.g address above bit39).
Hyper-V code may remap extra address space outside of swiotlb. swiotlb_bounce()
needs to use remap virtual address to copy data from
From: Tianyu Lan
Hyper-V exposes GHCB page via SEV ES GHCB MSR for SNP guest
to communicate with hypervisor. Map GHCB page for all
cpus to read/write MSR register and submit hvcall request
via GHCB.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/hv_init.c | 52
From: Tianyu Lan
The physical address of monitor pages in the CHANNELMSG_INITIATE_CONTACT
msg should be in the extra address space for SNP support and these
pages also should be accessed via the extra address space inside Linux
guest and remap the extra address by ioremap function.
Signed-off
From: Tianyu Lan
VMbus ring buffer are shared with host and it's need to
be accessed via extra address space of Isolation VM with
SNP support. This patch is to map the ring buffer
address in extra address space via ioremap(). HV host
visibility hvcall smears data in the ring buffer and
so
From: Tianyu Lan
Hyper-V provides two kinds of Isolation VMs. VBS(Virtualization-based
security) and AMD SEV-SNP unenlightened Isolation VMs. This patchset
is to add support for these Isolation VM support in Linux.
The memory of these vms are encrypted and host can't access guest
m
From: Tianyu Lan
Hyper-V provides GHCB protocol to write Synthetic Interrupt
Controller MSR registers and these registers are emulated by
Hypervisor rather than paravisor.
Hyper-V requests to write SINTx MSR registers twice(once via
GHCB and once via wrmsr instruction including the proxy bit 21
From: Tianyu Lan
In Isolation VM, all shared memory with host needs to mark visible
to host via hvcall. vmbus_establish_gpadl() has already done it for
netvsc rx/tx ring buffer. The page buffer used by vmbus_sendpacket_
mpb_desc() still need to handle. Use DMA API to map/umap these
memory during
From: Tianyu Lan
Hyper-V exposes shared memory boundary via cpuid HYPERV_
CPUID_ISOLATION_CONFIG and store it in the shared_gpa_
boundary of ms_hyperv struct. This prepares to share
memory with host for AMD SEV SNP guest.
Signed-off-by: Tianyu Lan
---
arch/x86/kernel/cpu/mshyperv.c | 2
From: Tianyu Lan
Hyper-V Isolation VM requires bounce buffer support. To use swiotlb
bounce buffer, add Hyper-V dma ops and use swiotlb functions in the
map and unmap callback.
Allocate bounce buffer in the Hyper-V code because bounce buffer
needs to be accessed via extra address space(e.g
From: Tianyu Lan
Hyper-V provides ghcb hvcall to handle VMBus
HVCALL_SIGNAL_EVENT and HVCALL_POST_MESSAGE
msg in SNP Isolation VM. Add such support.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/ivm.c | 69 +
arch/x86/include/asm/mshyperv.h | 1
From: Tianyu Lan
In Isolation VM, all shared memory with host needs to mark visible
to host via hvcall. vmbus_establish_gpadl() has already done it for
netvsc rx/tx ring buffer. The page buffer used by vmbus_sendpacket_
pagebuffer() still need to handle. Use DMA API to map/umap these
memory
From: Tianyu Lan
Add new hvcall guest address host visibility support. Mark vmbus
ring buffer visible to host when create gpadl buffer and mark back
to not visible when tear down gpadl buffer.
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/Makefile
From: Tianyu Lan
UIO HV driver should not load in the isolation VM for security reason.
Return ENOTSUPP in the hv_uio_probe() in the isolation VM.
Signed-off-by: Tianyu Lan
---
drivers/uio/uio_hv_generic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/uio/uio_hv_generic.c b
On 3/4/2021 1:21 AM, Vitaly Kuznetsov wrote:
Tianyu Lan writes:
From: Tianyu Lan
Hyper-V provides ghcb hvcall to handle VMBus
HVCALL_SIGNAL_EVENT and HVCALL_POST_MESSAGE
msg in SNP Isolation VM. Add such support.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/ivm.c | 69
On 3/4/2021 1:16 AM, Vitaly Kuznetsov wrote:
Tianyu Lan writes:
From: Tianyu Lan
Hyper-V provides GHCB protocol to write Synthetic Interrupt
Controller MSR registers and these registers are emulated by
Hypervisor rather than paravisor.
Hyper-V requests to write SINTx MSR registers twice
On 3/4/2021 12:58 AM, Vitaly Kuznetsov wrote:
Tianyu Lan writes:
From: Tianyu Lan
Add new hvcall guest address host visibility support. Mark vmbus
ring buffer visible to host when create gpadl buffer and mark back
to not visible when tear down gpadl buffer.
Signed-off-by: Sunil
Hi Vitaly:
Thanks for your review.
On 3/4/2021 12:27 AM, Vitaly Kuznetsov wrote:
Tianyu Lan writes:
From: Tianyu Lan
Add visibility parameter for vmbus_establish_gpadl() and prepare
to change host visibility when create gpadl for buffer.
"No functional change" as you don&
Hi Sunil:
Thanks for your review.
On 3/2/2021 3:45 AM, Sunil Muthuswamy wrote:
Hi Christoph:
Thanks a lot for your review. There are some reasons.
1) Vmbus drivers don't use DMA API now.
What is blocking us from making the Hyper-V drivers use the DMA API's? They
will be a nul
Hi Christoph:
Thanks a lot for your review. There are some reasons.
1) Vmbus drivers don't use DMA API now.
2) Hyper-V Vmbus channel ring buffer already play bounce buffer
role for most vmbus drivers. Just two kinds of packets from
netvsc/storvsc are uncovered.
3) In AMD SEV-
From: Tianyu Lan
Storvsc driver needs to reverse additional bounce
buffers to receive multipagebuffer packet and copy
data from brounce buffer when get response messge
from message.
Signed-off-by: Sunil Muthuswamy
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
drivers/scsi
From: Tianyu Lan
Add new parameter io_type and struct bounce_pkt for
vmbus_sendpacket_pagebuffer()
and vmbus_sendpacket_mpb_desc() in order to add bounce buffer support
later.
Signed-off-by: Sunil Muthuswamy
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
drivers/hv
From: Tianyu Lan
Hyper-V provides two kinds of Isolation VMs. VBS(Virtualization-based
security) and AMD SEV-SNP base Isolation VMs. The memory of these vms
are encrypted and host can't access guest memory directly. The
guest needs to call hv host visibility hvcall to mark memory visible
to
From: Tianyu Lan
Add Isolation VM support for netvsc driver. Map send/receive
ring buffer in extra address space in SNP isolation VM, reserve
bounce buffer for packets sent via vmbus_sendpacket_pagebuffer()
and release bounce buffer via hv_pkt_bounce() when get send
complete response from host
From: Tianyu Lan
The physical address of monitor pages in the CHANNELMSG_INITIATE_CONTACT
msg should be in the extra address space for SNP support and these
pages also should be accessed via the extra address space inside Linux
guest and remap the extra address by ioremap function.
Signed-off
From: Tianyu Lan
Initialize/free bounce buffer resource when add/delete
vmbus channel in Isolation VM.
Signed-off-by: Sunil Muthuswamy
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
drivers/hv/Makefile | 2 +-
drivers/hv/channel_mgmt.c | 29
From: Tianyu Lan
VMbus ring buffer are shared with host and it's need to
be accessed via extra address space of Isolation VM with
SNP support. This patch is to map the ring buffer
address in extra address space via ioremap(). HV host
visibility hvcall smears data in the ring buffer and
so
From: Tianyu Lan
Hyper-V provides ghcb hvcall to handle VMBus
HVCALL_SIGNAL_EVENT and HVCALL_POST_MESSAGE
msg in SNP Isolation VM. Add such support.
Signed-off-by: Tianyu Lan
---
arch/x86/hyperv/ivm.c | 69 +
arch/x86/include/asm/mshyperv.h | 1
From: Tianyu Lan
Hyper-V provides GHCB protocol to write Synthetic Interrupt
Controller MSR registers and these registers are emulated by
Hypervisor rather than paravisor.
Hyper-V requests to write SINTx MSR registers twice(once via
GHCB and once via wrmsr instruction including the proxy bit 21
From: Tianyu Lan
Hyper-V exposes GHCB page via SEV ES GHCB MSR for SNP guest
to communicate with hypervisor. Map GHCB page for all
cpus to read/write MSR register and submit hvcall request
via GHCB. Hyper-V also exposes shared memory boundary via
cpuid HYPERV_CPUID_ISOLATION_CONFIG and store it
From: Tianyu Lan
Hyper-V provides two kinds of Isolation VMs. VBS(Virtualization-based
security) and AMD SEV-SNP unenlightened Isolation VMs. This patchset
is to add support for these Isolation VM support in Linux.
The memory of these vms are encrypted and host can't access guest
m
From: Tianyu Lan
Add new hvcall guest address host visibility support. Mark vmbus
ring buffer visible to host when create gpadl buffer and mark back
to not visible when tear down gpadl buffer.
Signed-off-by: Sunil Muthuswamy
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
From: Tianyu Lan
Add visibility parameter for vmbus_establish_gpadl() and prepare
to change host visibility when create gpadl for buffer.
Signed-off-by: Sunil Muthuswamy
Co-Developed-by: Sunil Muthuswamy
Signed-off-by: Tianyu Lan
---
arch/x86/include/asm/hyperv-tlfs.h | 9
}
/* Note: when the ops are called, only CPU0 is online and IRQs are disabled. */
Reviewed-by: Tianyu Lan
On 10/10/2019 10:29 PM, Dave Hansen wrote:> On 10/10/19 12:28 AM,
lantianyu1...@gmail.com wrote:
>> When release mem region, old mem region may be splited to
>> two regions. Current allocate new struct resource for high
>> end mem region but not move child resources whose ranges are
>> in the high
PM
To: k...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org; Paolo Bonzini ; Radim
Krčmář ; Sean Christopherson
; Jim Mattson ; Tianyu
Lan
Subject: [PATCH] KVM: vmx: fix a build warning in hv_enable_direct_tlbflush()
on i386
The following was reported on i386:
arch
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 4030b4c585c41eeefec7bd20ce3d0e100a0f2e4d
Gitweb:
https://git.kernel.org/tip/4030b4c585c41eeefec7bd20ce3d0e100a0f2e4d
Author:Tianyu Lan
AuthorDate:Mon, 02 Sep 2019 20:41:43 +08:00
Committer
On Sat, Aug 31, 2019 at 1:41 AM Michael Kelley wrote:
>
> From: lantianyu1...@gmail.com Sent: Thursday, August 29, 2019 11:16 PM
> >
> > From: Tianyu Lan
> >
> > fill_gva_list() populates gva list and adds offset
> > HV_TLB_FLUSH_UNIT(0x100) to variable &
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 41cfe2a2a7f4fad5647031ad3a1da166452b5437
Gitweb:
https://git.kernel.org/tip/41cfe2a2a7f4fad5647031ad3a1da166452b5437
Author:Tianyu Lan
AuthorDate:Wed, 28 Aug 2019 16:07:47 +08:00
Committer
On Tue, Aug 27, 2019 at 8:38 PM Vitaly Kuznetsov wrote:
>
> Tianyu Lan writes:
>
> > On Tue, Aug 27, 2019 at 2:41 PM Vitaly Kuznetsov
> > wrote:
> >>
> >> lantianyu1...@gmail.com writes:
> >>
> >> > From: Tianyu Lan
> >&g
On Tue, Aug 27, 2019 at 2:41 PM Vitaly Kuznetsov wrote:
>
> lantianyu1...@gmail.com writes:
>
> > From: Tianyu Lan
> >
> > This patchset is to add Hyper-V direct tlb support in KVM. Hyper-V
> > in L0 can delegate L1 hypervisor to handle tlb flush request from
&
On Sun, Aug 25, 2019 at 1:52 AM Sasha Levin wrote:
>
> On Thu, Aug 22, 2019 at 10:39:46AM +0200, Vitaly Kuznetsov wrote:
> >lantianyu1...@gmail.com writes:
> >
> >> From: Tianyu Lan
> >>
> >> Both Hyper-V tsc page and Hyper-V tsc MSR code use variab
The following commit has been merged into the timers/core branch of tip:
Commit-ID: bd00cd52d5be655a2f217e2ed74b91a71cb2b14f
Gitweb:
https://git.kernel.org/tip/bd00cd52d5be655a2f217e2ed74b91a71cb2b14f
Author:Tianyu Lan
AuthorDate:Wed, 14 Aug 2019 20:32:16 +08:00
Committer
The following commit has been merged into the timers/core branch of tip:
Commit-ID: adb87ff4f96c9700718e09c97a804124d5cd61ff
Gitweb:
https://git.kernel.org/tip/adb87ff4f96c9700718e09c97a804124d5cd61ff
Author:Tianyu Lan
AuthorDate:Wed, 14 Aug 2019 20:32:15 +08:00
Committer
On Thu, Aug 22, 2019 at 4:39 PM Vitaly Kuznetsov wrote:
>
> lantianyu1...@gmail.com writes:
>
> > From: Tianyu Lan
> >
> > Both Hyper-V tsc page and Hyper-V tsc MSR code use variable
> > hv_sched_clock_offset for their sched clock callback and so
>
Thanks for reporting. I will send out fix patch.
-Original Message-
From: kbuild test robot
Sent: Thursday, August 22, 2019 10:25 AM
To: Tianyu Lan
Cc: kbuild-...@01.org; linux-kernel@vger.kernel.org; tipbu...@zytor.com; Thomas
Gleixner ; Michael Kelley
Subject: [tip:timers/core 34
Hi Thomas:
Thanks for your review. Will fix your comment in the
next version.
On Mon, Aug 19, 2019 at 9:27 PM Thomas Gleixner wrote:
>
> On Mon, 19 Aug 2019, lantianyu1...@gmail.com wrote:
>
> > From: Tianyu Lan
> >
> > This patch adds
>
>
; };
> >
> > #define kvm_err(fmt, ...) \
>
> This does not exist on non-x86 architectures. Please move it to struct
> kvm_arch.
>
Nice catch. Will update in the next version. Thanks.
--
Best regards
Tianyu Lan
: Denis Efremov ; j...@perches.com; Tianyu Lan
; Sasha Levin ;
linux-hyp...@vger.kernel.org
Subject: [PATCH] MAINTAINERS: Hyper-V: Fix typo in a filepath
Fix typo in hyperv-iommu.c filepath.
Cc: Lan Tianyu
Cc: Sasha Levin
Cc: linux-hyp...@vger.kernel.org
Fixes: 29217a474683 ("iommu/hyper-v
Hi Vitaly & Peter:
Thanks for your review.
On Mon, Jul 29, 2019 at 8:13 PM Vitaly Kuznetsov wrote:
>
> Peter Zijlstra writes:
>
> > On Mon, Jul 29, 2019 at 12:59:26PM +0200, Vitaly Kuznetsov wrote:
> >> lantianyu1...@gmail.com writes:
> >>
> >
st->state++;
> ret = cpuhp_invoke_callback(cpu, st->state, true, NULL, NULL);
> if (ret) {
> - st->target = prev_state;
> - undo_cpu_up(cpu, st);
> + if (can_rollback_cpu(st)) {
> + st->target = prev_state;
> + undo_cpu_up(cpu, st);
> + }
> break;
> }
> }
>
I have tested your patch. It resolves the crash with "nosmt" parameter.
--
Best regards
Tianyu Lan
Kelley ; Tianyu
Lan ; Joerg Roedel
Subject: Bad file pattern in MAINTAINERS section 'Hyper-V CORE AND DRIVERS'
A file pattern line in this section of the MAINTAINERS file in linux-next does
not have a match in the linux source files.
This could occur because a matching filename was never
Add Hyper-V stub IOMMU driver
> > MAINTAINERS: Add Hyper-V IOMMU driver into Hyper-V CORE AND DRIVERS
> > scope
>
> Applied (patch 2 with slight subject changes
> 'HYPERV/IOMMU' -> 'iommu/hyper-v'), thanks.
Great. Thanks.
--
Best regards
Tianyu Lan
e better?
Yes, this makes sense. Will update. Thanks.
--
Best regards
Tianyu Lan
> support")
>
> "Fixes"
Sorry, fix this in the V2.
--
Best regards
Tianyu Lan
chset is based on the fix patch "x86/Hyper-V: Fix definition
> > HV_MAX_FLUSH_REP_COUNT".
> > (https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1939455.html)
>
> Note that this won't make it in 5.1 unless Linus releases an -rc8.
> Otherwise, I'll get to it next week.
Hi Paolo:
Sure. Thanks for your review.
--
Best regards
Tianyu Lan
quot;%s\")%n"
>
OK. Will update. Thanks.
> You also messed up your To: line, keeping anyone from being able to
> respond to this message who do not know how to hand-edit the response
> line :(
I put all expected reviewers in the Cc line and will put into To line.
>
> thanks,
>
> greg k-h
--
Best regards
Tianyu Lan
On Fri, Feb 15, 2019 at 11:23 PM Paolo Bonzini wrote:
>
> On 15/02/19 16:05, Tianyu Lan wrote:
> > Yes, you are right. Thanks to point out and will fix. The last_level
> > flag is to avoid adding middle page node(e.g, PGD, PMD)
> > into flush list. The address range will
Hi Michael:
Thanks for your review.
-Original Message-
From: Michael Kelley
Sent: Friday, February 22, 2019 1:28 AM
To: lantianyu1...@gmail.com
Cc: Tianyu Lan ; j...@8bytes.org;
mchehab+sams...@kernel.org; da...@davemloft.net; gre...@linuxfoundation.org;
nicolas.fe
e node into flush list.
>
> Thanks,
>
> Paolo
>
> > if (tdp_enabled)
> > spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
> > kvm_is_mmio_pfn(pfn));
>
--
Best regards
Tianyu Lan
t; + depends on HYPERV
> > + select IOMMU_API
> > + help
>
>
> Consider adding 'default HYPERV' like some other drivers already do it.
>
> Olaf
Good suggestion and will update. Thanks.
--
Best regards
Tianyu Lan
gt; > + return 0;
> > +}
> > +
> > +static int __init hyperv_enable_irq_remapping(void)
> > +{
> > + return IRQ_REMAP_X2APIC_MODE;
> > +}
> > +
> > +static struct irq_domain *hyperv_get_ir_irq_domain(struct irq_alloc_info
> > *info)
> > +{
> > + if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC)
> > + return ioapic_ir_domain;
> > + else
> > + return NULL;
> > +}
> > +
> > +struct irq_remap_ops hyperv_irq_remap_ops = {
> > + .prepare= hyperv_prepare_irq_remapping,
> > + .enable = hyperv_enable_irq_remapping,
> > + .get_ir_irq_domain = hyperv_get_ir_irq_domain,
> > +};
> > +
> > +#endif
> > diff --git a/drivers/iommu/irq_remapping.c b/drivers/iommu/irq_remapping.c
> > index b94ebd4..81cf290 100644
> > --- a/drivers/iommu/irq_remapping.c
> > +++ b/drivers/iommu/irq_remapping.c
> > @@ -103,6 +103,9 @@ int __init irq_remapping_prepare(void)
> > else if (IS_ENABLED(CONFIG_AMD_IOMMU) &&
> >amd_iommu_irq_ops.prepare() == 0)
> > remap_ops = &amd_iommu_irq_ops;
> > + else if (IS_ENABLED(CONFIG_HYPERV_IOMMU) &&
> > + hyperv_irq_remap_ops.prepare() == 0)
> > + remap_ops = &hyperv_irq_remap_ops;
> > else
> > return -ENOSYS;
> >
> > diff --git a/drivers/iommu/irq_remapping.h b/drivers/iommu/irq_remapping.h
> > index 0afef6e..f8609e9 100644
> > --- a/drivers/iommu/irq_remapping.h
> > +++ b/drivers/iommu/irq_remapping.h
> > @@ -64,6 +64,7 @@ struct irq_remap_ops {
> >
> > extern struct irq_remap_ops intel_irq_remap_ops;
> > extern struct irq_remap_ops amd_iommu_irq_ops;
> > +extern struct irq_remap_ops hyperv_irq_remap_ops;
> >
> > #else /* CONFIG_IRQ_REMAP */
>
> --
> Vitaly
--
Best regards
Tianyu Lan
le on Hyper-v are sorted monotonic increasingly.
> > + * APIC ID reflects cpu topology. There maybe some APIC ID
> > + * gaps when cpu number in a socket is not power of two. Prepare
> > + * max cpu affinity for IOAPIC irqs. Scan cpu 0-255 and set cpu
> > + * into ioapic_max_cpumask if its APIC ID is less than 256.
> > + */
> > + for (i = 0; i < 256; i++)
> > + if (cpu_physical_id(i) < 256)
> > + cpumask_set_cpu(i, &ioapic_max_cpumask);
>
> This looks sketchy. What if NR_CPUS is less than 256? Thanks,
Nice catch. I should check NR_CPUS here. Will update. Thanks.
--
Best regards
Tianyu Lan
the latter:
>
>Reviewed-by: Thomas Gleixner
>
> If not, I just queue if for 5.1. Let me know,
>
This patch can be applied independently. Thanks.
--
Best regards
Tianyu Lan
u(i, &ioapic_max_cpumask);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __init hyperv_enable_irq_remapping(void)
> > +{
> > + return IRQ_REMAP_X2APIC_MODE;
> > +}
> > +
> > +static struct irq_domain *hyperv_get_ir_irq_domain(struct irq_alloc_info
> > *info)
> > +{
> > + if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC)
> > + return ioapic_ir_domain;
> > + else
> > + return NULL;
> > +}
> > +
> > +struct irq_remap_ops hyperv_irq_remap_ops = {
> > + .prepare= hyperv_prepare_irq_remapping,
> > + .enable = hyperv_enable_irq_remapping,
> > + .get_ir_irq_domain = hyperv_get_ir_irq_domain,
> > +};
> > diff --git a/drivers/iommu/irq_remapping.c b/drivers/iommu/irq_remapping.c
> > index b94ebd4..81cf290 100644
> > --- a/drivers/iommu/irq_remapping.c
> > +++ b/drivers/iommu/irq_remapping.c
> > @@ -103,6 +103,9 @@ int __init irq_remapping_prepare(void)
> > else if (IS_ENABLED(CONFIG_AMD_IOMMU) &&
> >amd_iommu_irq_ops.prepare() == 0)
> > remap_ops = &amd_iommu_irq_ops;
> > + else if (IS_ENABLED(CONFIG_HYPERV_IOMMU) &&
> > + hyperv_irq_remap_ops.prepare() == 0)
> > + remap_ops = &hyperv_irq_remap_ops;
> > else
> > return -ENOSYS;
> >
> > diff --git a/drivers/iommu/irq_remapping.h b/drivers/iommu/irq_remapping.h
> > index 0afef6e..f8609e9 100644
> > --- a/drivers/iommu/irq_remapping.h
> > +++ b/drivers/iommu/irq_remapping.h
> > @@ -64,6 +64,7 @@ struct irq_remap_ops {
> >
> > extern struct irq_remap_ops intel_irq_remap_ops;
> > extern struct irq_remap_ops amd_iommu_irq_ops;
> > +extern struct irq_remap_ops hyperv_irq_remap_ops;
> >
> > #else /* CONFIG_IRQ_REMAP */
> >
> >
--
Best regards
Tianyu Lan
t; >+
> >+static int __init hyperv_enable_irq_remapping(void)
> >+{
> >+ return IRQ_REMAP_X2APIC_MODE;
> >+}
> >+
> >+static struct irq_domain *hyperv_get_ir_irq_domain(struct irq_alloc_info
> >*info)
> >+{
> >+ if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC)
> >+ return ioapic_ir_domain;
> >+ else
> >+ return NULL;
> >+}
> >+
> >+struct irq_remap_ops hyperv_irq_remap_ops = {
> >+ .prepare= hyperv_prepare_irq_remapping,
> >+ .enable = hyperv_enable_irq_remapping,
> >+ .get_ir_irq_domain = hyperv_get_ir_irq_domain,
> >+};
> >diff --git a/drivers/iommu/irq_remapping.c b/drivers/iommu/irq_remapping.c
> >index b94ebd4..81cf290 100644
> >--- a/drivers/iommu/irq_remapping.c
> >+++ b/drivers/iommu/irq_remapping.c
> >@@ -103,6 +103,9 @@ int __init irq_remapping_prepare(void)
> > else if (IS_ENABLED(CONFIG_AMD_IOMMU) &&
> >amd_iommu_irq_ops.prepare() == 0)
> > remap_ops = &amd_iommu_irq_ops;
> >+ else if (IS_ENABLED(CONFIG_HYPERV_IOMMU) &&
> >+ hyperv_irq_remap_ops.prepare() == 0)
> >+ remap_ops = &hyperv_irq_remap_ops;
> > else
> > return -ENOSYS;
> >
> >diff --git a/drivers/iommu/irq_remapping.h b/drivers/iommu/irq_remapping.h
> >index 0afef6e..f8609e9 100644
> >--- a/drivers/iommu/irq_remapping.h
> >+++ b/drivers/iommu/irq_remapping.h
> >@@ -64,6 +64,7 @@ struct irq_remap_ops {
> >
> > extern struct irq_remap_ops intel_irq_remap_ops;
> > extern struct irq_remap_ops amd_iommu_irq_ops;
> >+extern struct irq_remap_ops hyperv_irq_remap_ops;
> >
> > #else /* CONFIG_IRQ_REMAP */
> >
> >--
> >2.7.4
> >
--
Best regards
Tianyu Lan
fn = irq_domain_alloc_named_id_fwnode("HYPERV-IR", 0);
> > + if (!fn)
> > + return -EFAULT;
>
> Why does this return -EFAULT? I guess there is no fault happening in
> irq_domain_alloc_named_id_fwnode()...
Yes, “-ENOMEM” should be more accurate.
--
Best regards
Tianyu Lan
ed())
> x2apic_phys = 1;
>
> It works the same and is slightly more pleasant to look at.
Yes, that will better. Thanks for your suggestion. Dan
--
Best regards
Tianyu Lan
Hi Vitaly:
Thanks for your review.
On Thu, Jan 31, 2019 at 10:04 PM Vitaly Kuznetsov wrote:
>
> lantianyu1...@gmail.com writes:
>
> > From: Lan Tianyu
> >
> > On the bare metal, enabling X2APIC mode requires interrupt remapping
> > function which helps to deliver irq to cpu with 32-b
t; +static cpumask_t ioapic_max_cpumask = { CPU_BITS_NONE };
> > +struct irq_domain *ioapic_ir_domain;
>
> Global? Why?
It should be "static" here.
--
Best regards
Tianyu Lan
t; @@ -36,6 +36,8 @@
> > struct ms_hyperv_info ms_hyperv;
> > EXPORT_SYMBOL_GPL(ms_hyperv);
> >
> > +extern int x2apic_phys;
>
> Shouldn't this be in a .h file somewhere instead?
You are right. I should use here. Thanks.
> thanks,
>
> greg k-h
--
Best regards
Tianyu Lan
ould share more code, not
> less).
kvm_vm_ioctl_clear_dirty_log/get_dirty_log() is to get/clear dirty log with
memslot as unit. We may just flush tlbs of the affected memslot instead of
entire page table's when range flush is available.
>
> Paolo
>
> > + flush = false;
> > + }
> > +
>
--
Best regards
Tianyu Lan
Hi Paolo:
Thanks for your review.
On Tue, Jan 8, 2019 at 12:31 AM Paolo Bonzini wrote:
>
> On 07/01/19 04:42, Tianyu Lan wrote:
> >> I'm assuming you're
> >> clearing young to avoid the flush in kvm_mmu_notifier_clear_flush_young(),
> >&g
kvm);
> > + kvm_flush_remote_tlbs_with_list(vcpu->kvm, &flush_list);
>
> This is a bit confusing and potentially fragile. It's not obvious that
> kvm_flush_remote_tlbs_with_list() is guaranteed to call
> kvm_flush_remote_tlbs() when kvm_available_flush_tlb_with_range() is
> false, and you're relying on the kvm_flush_remote_tlbs_with_list() call
> chain to never optimize away the empty list case. Rechecking
> kvm_available_flush_tlb_with_range() isn't expensive.
That makes sense. Will update. Thanks.
>
> >
> > return nr_present;
> > }
> > --
> > 2.14.4
> >
--
Best regards
Tianyu Lan
platforms still need the
flush in the
kvm_mmu_notifier_clear_flush_young(). I think it's better to separate
flush request and
"young" from return value of kvm_age_hva(). New flush parameter I
added in the patch 10
can be changed to a pointer and kvm_age_hva() can use it to return
flush request.
--
Best regards
Tianyu Lan
; @@ -11614,6 +11621,8 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm
> > *kvm, unsigned int id)
> > vmx->pi_desc.nv = POSTED_INTR_VECTOR;
> > vmx->pi_desc.sn = 1;
> >
> > + vmx->ept_pointer = INVALID_PAGE;
> > +
> > return &vmx->vcpu;
> >
> > free_vmcs:
> >
>
--
Best regards
Tianyu Lan
OK. Thanks for suggestion and will update in the next version.
>
> > Signed-off-by: Lan Tianyu
>
> For the powerpc bits:
>
> Acked-by: Paul Mackerras
--
Best regards
Tianyu Lan
On 11/7/2018 6:49 PM, Vitaly Kuznetsov wrote:
Tianyu Lan writes:
Hi Vitaly:
Thanks for your review.
On 11/6/2018 11:50 PM, Vitaly Kuznetsov wrote:
ltyker...@gmail.com writes:
From: Lan Tianyu
This patch is to initialize ept_pointer to INVALID_PAGE and check it
before flushing
Hi Vitaly:
Thanks for your review.
On 11/6/2018 11:50 PM, Vitaly Kuznetsov wrote:
ltyker...@gmail.com writes:
From: Lan Tianyu
This patch is to initialize ept_pointer to INVALID_PAGE and check it
before flushing ept tlb. If ept_pointer is invalidated, bypass the flush
request.
Signe
gt; }
> > }
> >
> > + if (flush && kvm_available_flush_tlb_with_range())
> > + kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
> > + gfn_end - gfn_start + 1);
> > +
>
> ... and this can be just if (flush), because if flush_tlb is true then
> slot_handle_level_range always returns false.
OK. Will update.
--
Best regards
Tianyu Lan
On Thu, Oct 11, 2018 at 9:00 PM Vitaly Kuznetsov wrote:
>
> Tianyu Lan writes:
>
> > On Thu, Oct 11, 2018 at 8:18 PM Vitaly Kuznetsov
> > wrote:
> >>
> >> Tianyu Lan writes:
> >>
> >> > On Thu, Oct 11, 2018 at 6:32 PM Vitaly Ku
1 - 100 of 232 matches
Mail list logo
