On 9/20/2019 4:31 PM, Uwe Kleine-König wrote:
> According to Tal Gilboa the only benefit from DIM comes from a driver
> that uses it. So it doesn't make sense to make this symbol user visible,
> instead all drivers that use it should select it (as is already the case
> AFAICT).
&
On 9/20/2019 12:07 AM, Uwe Kleine-König wrote:
> On 9/19/19 11:03 PM, Uwe Kleine-König wrote:
>> Fixes: 4f75da3666c0 ("linux/dim: Move implementation to .c files")
>> Signed-off-by: Uwe Kleine-König
>> ---
>> lib/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git
On 8/8/2018 6:41 PM, Leon Romanovsky wrote:
On Wed, Aug 08, 2018 at 05:23:12PM +0300, Tal Gilboa wrote:
On 8/8/2018 9:08 AM, Leon Romanovsky wrote:
On Mon, Aug 06, 2018 at 06:25:42PM -0500, Alexandru Gagniuc wrote:
This is now done by the PCI core to warn of sub-optimal bandwidth.
Signed-off
On 7/31/2018 6:10 PM, Alex G. wrote:
On 07/31/2018 01:40 AM, Tal Gilboa wrote:
[snip]
@@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct
pci_dev *dev)
/* Advanced Error Reporting */
pci_aer_init(dev);
+ /* Check link and detect downtrain errors
On 7/24/2018 12:52 AM, Tal Gilboa wrote:
On 7/24/2018 12:01 AM, Jakub Kicinski wrote:
On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or higher speed than negotiated.
Downtraining might
On 7/24/2018 2:59 AM, Alex G. wrote:
On 07/23/2018 05:14 PM, Jakub Kicinski wrote:
On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote:
On 7/24/2018 12:01 AM, Jakub Kicinski wrote:
On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device
On 7/24/2018 12:01 AM, Jakub Kicinski wrote:
On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or higher speed than negotiated.
Downtraining might be indicative of other problems in the syst
On 7/23/2018 8:01 PM, Alex G. wrote:
On 07/23/2018 12:21 AM, Tal Gilboa wrote:
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe share the same link/status. */
+ if
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On Mon, Jun 04, 2018 at 10:55:21AM -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or hi
On 4/5/2018 4:13 PM, Geert Uytterhoeven wrote:
Hi Tal,
With gcc-4.1.2:
drivers/net/ethernet/broadcom/bcmsysport.c: In function ‘bcm_sysport_poll’:
include/linux/net_dim.h:354: warning: ‘curr_stats.ppms’ may be
used uninitialized in this function
include/linux/net_dim.h:354: warni
On 4/2/2018 11:25 PM, Keller, Jacob E wrote:
-Original Message-
From: Bjorn Helgaas [mailto:helg...@kernel.org]
Sent: Monday, April 02, 2018 12:58 PM
To: Keller, Jacob E
Cc: Tal Gilboa ; Tariq Toukan ; Ariel
Elior ; Ganesh Goudar ;
Kirsher, Jeffrey T ; everest-linux...@cavium.com
On 4/2/2018 5:05 PM, Bjorn Helgaas wrote:
On Mon, Apr 02, 2018 at 10:34:58AM +0300, Tal Gilboa wrote:
On 4/2/2018 3:40 AM, Bjorn Helgaas wrote:
On Sun, Apr 01, 2018 at 11:38:53PM +0300, Tal Gilboa wrote:
On 3/31/2018 12:05 AM, Bjorn Helgaas wrote:
From: Tal Gilboa
Add
On 4/2/2018 3:40 AM, Bjorn Helgaas wrote:
On Sun, Apr 01, 2018 at 11:38:53PM +0300, Tal Gilboa wrote:
On 3/31/2018 12:05 AM, Bjorn Helgaas wrote:
From: Tal Gilboa
Add pcie_bandwidth_capable() to compute the max link bandwidth supported by
a device, based on the max link speed and width
On 3/31/2018 12:05 AM, Bjorn Helgaas wrote:
From: Tal Gilboa
Add pcie_bandwidth_available() to compute the bandwidth available to a
device. This may be limited by the device itself or by a slower upstream
link leading to the device.
The available bandwidth at each link along the path is
On 3/31/2018 12:05 AM, Bjorn Helgaas wrote:
From: Tal Gilboa
Add pcie_bandwidth_capable() to compute the max link bandwidth supported by
a device, based on the max link speed and width, adjusted by the encoding
overhead.
The maximum bandwidth of the link is computed as:
max_link_speed
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