Re: [PATCH 2/2] iommu/amd: Remove performance counter pre-initialization test

David / Joerg, On 4/10/2021 5:03 PM, David Coe wrote: The immediately obvious difference is the with the enormous count seen on mem_dte_mis on the older Ryzen 2400G. Will do some RTFM but anyone with  comments and insight? 841,689,151,202,939   amd_iommu_0/mem_dte_mis/  (33.44

Re: [PATCH 2/2] iommu/amd: Remove performance counter pre-initialization test

David, On 4/14/2021 10:33 PM, David Coe wrote: Hi Suravee! I've re-run your revert+update patch on Ubuntu's latest kernel 5.11.0-14 partly to check my mailer's 'mangling' hadn't also reached the code! There are 3 sets of results in the attachment, all for the Ryzen 2400G. The as-distributed

Re: [PATCH 2/2] iommu/amd: Remove performance counter pre-initialization test

On 4/10/2021 5:03 PM, David Coe wrote: Results for AMD Ryzen 4700U running Ubuntu 21.04β kernel 5.11.0-13 $ sudo dmesg | grep IOMMU [    0.490352] pci :00:00.2: AMD-Vi: IOMMU performance counters supported [    0.491985] pci :00:00.2: AMD-Vi: Found IOMMU cap 0x40 [    0.493732] perf/a

Re: [PATCH 1/2] Revert "iommu/amd: Fix performance counter initialization"

Shuah, On 4/10/2021 12:06 AM, Shuah Khan wrote: diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 321f5906e6ed..648cdfd03074 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1729,39 +1728,17 @@ static void __init init_iommu_perf_ctr(struct amd_io

Re: IOMMU vs Ryzen embedded EMMC controller

Hi, On 10/9/19 2:25 PM, Jiri Kosina wrote: > On Fri, 27 Sep 2019, Shah, Nehal-bakulchandra wrote: > > Do you have BAR memory allocation failures in dmesg with IOMMU on? >>> >>> No. The device is *not* treated as PCI device and I still think that >>> this is the source of the evil. >>> > A

Re: [PATCH v3 00/16] kvm: x86: Support AMD SVM AVIC w/ in-kernel irqchip mode

Ping: Hi All, Are there other concerns or suggestions for this series? Thanks, Suravee On 9/13/19 2:00 PM, Suthikulpanit, Suravee wrote: > The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before > enabling AVIC")' was introduced to fix miscellaneo

[PATCH v3 06/16] kvm: x86: svm: Add support to activate/deactivate posted interrupts

Introduce interface for activate/deactivate posted interrupts, and implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 4 arch/x86/kvm/svm.c | 44 +

[PATCH v3 11/16] svm: Temporary deactivate AVIC during ExtINT handling

AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary deactivated and fall back to using legacy interrupt injection via vINTR and interrupt window. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 50 ++ 1 file changed, 4

[PATCH v3 04/16] kvm: x86: Add support for activate/de-activate APICv at runtime

Certain runtime conditions require APICv to be temporary deactivated. However, current implementation only support permanently deactivate APICv at runtime (mainly used when running Hyper-V guest). In addition, for AMD, when activate / deactivate APICv during runtime, all vcpus in the VM has to be

[PATCH v3 13/16] kvm: lapic: Clean up APIC predefined macros

Move these duplicated predefined macros to the header file so that it can be re-used in other places. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/lapic.c | 13 + arch/x86/kvm/lapic.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/lapic.c

[PATCH v3 07/16] svm: Add support for setup/destroy virutal APIC backing page for AVIC

Activate/deactivate AVIC requires setting/unsetting the memory region used for virtual APIC backing page (APIC_ACCESS_PAGE_PRIVATE_MEMSLOT). So, re-factor avic_init_access_page() to avic_setup_access_page() and add srcu_read_lock/unlock, which are needed to allow this function to be called during r

[PATCH v3 14/16] kvm: ioapic: Refactor kvm_ioapic_update_eoi()

Refactor code for handling IOAPIC EOI for subsequent patch. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/ioapic.c | 110 +- 1 file changed, 56 insertions(+), 54 deletions(-) diff --git a/arch/x86/kvm/ioapic.

[PATCH v3 09/16] kvm: x86: hyperv: Use APICv deactivate request interface

Since disabling APICv has to be done for all vcpus on AMD-based system, adopt the newly introduced kvm_make_apicv_deactivate_request() interface. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/hyperv.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/

[PATCH v3 15/16] kvm: x86: ioapic: Lazy update IOAPIC EOI

In-kernel IOAPIC does not receive EOI with AMD SVM AVIC since the processor accelerate write to APIC EOI register and does not trap if the interrupt is edge-triggered. Workaround this by lazy check for pending APIC EOI at the time when setting new IOPIC irq, and update IOAPIC EOI if no pending API

[PATCH v3 10/16] svm: Disable AVIC when launching guest with SVM support

Since AVIC does not currently work w/ nested virtualization, disable AVIC for the guest if setting CPUID Fn8001_ECX[SVM] (i.e. indicate support for SVM, which is needed for nested virtualization). Suggested-by: Alexander Graf Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 10

[PATCH v3 16/16] svm: Allow AVIC with in-kernel irqchip mode

Once run-time AVIC activate/deactivate is supported, and EOI workaround for AVIC is implemented, we can remove the kernel irqchip split mode requirement for AVIC. Hence, remove the check for irqchip split mode when enabling AVIC. Cc: Radim Krčmář Cc: Paolo Bonzini Signed-off-by: Suravee Suthiku

[PATCH v3 12/16] kvm: x86: Introduce struct kvm_x86_ops.apicv_eoi_accelerate

AMD SVM AVIC accelerates write access to APIC EOI register for edge-trigger interrupts, and does not trap. This breaks in-kernel irqchip, which expects the EOI trap to send notifier for acked irq. Introduce struct kvm_x86_ops.apicv_eoi_accelerate to allow check for such behavior. Signed-off-by: S

[PATCH v3 05/16] kvm: x86: Add APICv activate/deactivate request trace points

Add trace points when sending request to activate/deactivate APICv. Suggested-by: Alexander Graf Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/trace.h | 30 ++ arch/x86/kvm/x86.c | 7 +++ 2 files changed, 37 insertions(+) diff --git a/arch/x86/kvm/tra

[PATCH v3 00/16] kvm: x86: Support AMD SVM AVIC w/ in-kernel irqchip mode

The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before enabling AVIC")' was introduced to fix miscellaneous boot-hang issues when enable AVIC. This is mainly due to AVIC hardware doest not #vmexit on write to LAPIC EOI register resulting in-kernel PIC and IOAPIC to wait and do not i

[PATCH v3 08/16] svm: Add support for activate/deactivate AVIC at runtime

Add necessary logics for supporting activate/deactivate AVIC at runtime. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 27 +-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 2e06ee2..a01bc6a 100

[PATCH v3 01/16] kvm: x86: Modify kvm_x86_ops.get_enable_apicv() to use struct kvm parameter

Generally, APICv for all vcpus in the VM are enable/disable in the same manner. So, get_enable_apicv() should represent APICv status of the VM instead of each VCPU. Modify kvm_x86_ops.get_enable_apicv() to take struct kvm as parameter instead of struct kvm_vcpu. Reviewed-by: Vitaly Kuznetsov Sig

[PATCH v3 02/16] kvm: x86: Introduce KVM APICv state

Currently, after a VM boots with APICv enabled, it could go into the following states: * activated = VM is running w/ APICv * suspended = VM deactivate APICv temporarily * disabled = VM deactivate APICv permanently Introduce KVM APICv state enum to help keep track of the APICv states along

[PATCH v3 03/16] kvm: lapic: Introduce APICv update helper function

Re-factor code into a helper function for setting lapic parameters when activate/deactivate APICv, and export the function for subsequent usage. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/lapic.c | 22 +- arch/x86/kvm/lapic.h | 1 + 2 files changed, 18 insertions(

Re: [PATCH v2 12/15] kvm: i8254: Check LAPIC EOI pending when injecting irq on SVM AVIC

Alex, On 8/27/19 4:10 AM, Alexander Graf wrote: > > On 26.08.19 22:46, Suthikulpanit, Suravee wrote: >> Alex, >> >> On 8/19/2019 5:42 AM, Alexander Graf wrote: >>> >>> >>> On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >>>> ACK n

Re: [PATCH v2 11/15] svm: Temporary deactivate AVIC during ExtINT handling

Alex, On 8/28/19 2:37 PM, Graf (AWS), Alexander wrote: @@ -5522,9 +5558,6 @@ static void enable_irq_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); -if (kvm_vcpu_apicv_active(vcpu)) -return; - /*

Re: [PATCH v2 14/15] kvm: ioapic: Delay update IOAPIC EOI for RTC

Alex, On 8/19/19 6:00 AM, Alexander Graf wrote: > > > On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >> In-kernel IOAPIC does not update RTC pending EOI info with AMD SVM /w >> AVIC >> when interrupt is delivered as edge-triggered since AMD processors >

Re: [PATCH v2 04/15] kvm: x86: Add per-VM APICv state debugfs

Alex, On 8/27/19 3:20 AM, Alexander Graf wrote: > > > On 26.08.19 21:41, Suthikulpanit, Suravee wrote: >> Alex, >> >> On 8/19/2019 4:57 AM, Alexander Graf wrote: >>> >>> >>> On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >>>>

Re: [PATCH v2 11/15] svm: Temporary deactivate AVIC during ExtINT handling

Alex, On 8/19/19 5:35 AM, Alexander Graf wrote: > > > On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >> AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary >> deactivated and fall back to using legacy interrupt injection via vINTR >> and interrupt

Re: [PATCH v2 12/15] kvm: i8254: Check LAPIC EOI pending when injecting irq on SVM AVIC

Alex, On 8/19/2019 5:42 AM, Alexander Graf wrote: > > > On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >> ACK notifiers don't work with AMD SVM w/ AVIC when the PIT interrupt >> is delivered as edge-triggered fixed interrupt since AMD processors >> cannot 

Re: [PATCH v2 04/15] kvm: x86: Add per-VM APICv state debugfs

Alex, On 8/19/2019 4:57 AM, Alexander Graf wrote: > > > On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >> Currently, there is no way to tell whether APICv is active >> on a particular VM. This often cause confusion since APICv >> can be deactivated at runtime. >

Re: [PATCH v2 02/15] kvm: x86: Introduce KVM APICv state

Alex, On 8/19/2019 4:49 AM, Alexander Graf wrote: > > > On 15.08.19 18:25, Suthikulpanit, Suravee wrote: >> Currently, after a VM boots with APICv enabled, it could go into >> the following states: >>    * activated   = VM is running w/ APICv >>    * deactivated

[PATCH v2 02/15] kvm: x86: Introduce KVM APICv state

Currently, after a VM boots with APICv enabled, it could go into the following states: * activated = VM is running w/ APICv * deactivated = VM deactivate APICv (temporary) * disabled= VM deactivate APICv (permanent) Introduce KVM APICv state enum to help keep track of the APICv states

[PATCH v2 09/15] svm: Add support for activate/deactivate AVIC at runtime

Add necessary logics for supporting activate/deactivate AVIC at runtime. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 27 +-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 47f2439..cfa4b13 100

[PATCH v2 13/15] kvm: lapic: Clean up APIC predefined macros

Move these duplicated predefined macros to the header file so that it can be re-used in other places. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/lapic.c | 13 + arch/x86/kvm/lapic.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/lapic.c

[PATCH v2 14/15] kvm: ioapic: Delay update IOAPIC EOI for RTC

In-kernel IOAPIC does not update RTC pending EOI info with AMD SVM /w AVIC when interrupt is delivered as edge-triggered since AMD processors cannot exit on EOI for these interrupts. Add code to also check LAPIC pending EOI before injecting any new RTC interrupts on AMD SVM when AVIC is activated.

[PATCH v2 08/15] svm: Add support for setup/destroy virutal APIC backing page for AVIC

Activate/deactivate AVIC requires setting/unsetting the memory region used for virtual APIC backing page (APIC_ACCESS_PAGE_PRIVATE_MEMSLOT). So, re-factor avic_init_access_page() to avic_setup_access_page() and add srcu_read_lock/unlock, which are needed to allow this function to be called during r

[PATCH v2 05/15] kvm: lapic: Introduce APICv update helper function

Re-factor code into a helper function for setting lapic parameters when activate/deactivate APICv, and export the function for subsequent usage. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/lapic.c | 22 +- arch/x86/kvm/lapic.h | 1 + 2 files changed, 18 insertions(

[PATCH v2 04/15] kvm: x86: Add per-VM APICv state debugfs

Currently, there is no way to tell whether APICv is active on a particular VM. This often cause confusion since APICv can be deactivated at runtime. Introduce a debugfs entry to report APICv state of a VM. This creates a read-only file: /sys/kernel/debug/kvm/70860-14/apicv-state Signed-off-by

[PATCH v2 12/15] kvm: i8254: Check LAPIC EOI pending when injecting irq on SVM AVIC

ACK notifiers don't work with AMD SVM w/ AVIC when the PIT interrupt is delivered as edge-triggered fixed interrupt since AMD processors cannot exit on EOI for these interrupts. Add code to check LAPIC pending EOI before injecting any pending PIT interrupt on AMD SVM when AVIC is activated. Signe

[PATCH v2 06/15] kvm: x86: Add support for activate/de-activate APICv at runtime

Certain runtime conditions require APICv to be temporary deactivated. However, current implementation only support permanently deactivate APICv at runtime (mainly used when running Hyper-V guest). In addtion, for AMD, when activate / deactivate APICv during runtime, all vcpus in the VM has to be o

[PATCH v2 11/15] svm: Temporary deactivate AVIC during ExtINT handling

AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary deactivated and fall back to using legacy interrupt injection via vINTR and interrupt window. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 49 + 1 file changed, 45

[PATCH v2 15/15] svm: Allow AVIC with in-kernel irqchip mode

Once run-time AVIC activate/deactivate, and PIC and IOAPIC EOI workaround for AVIC is supported, we can remove the kernel irqchip split mode requirement for AVIC. Hence, remove the check for irqchip split mode when enabling AVIC. Cc: Radim Krčmář Cc: Paolo Bonzini Signed-off-by: Suravee Suthiku

[PATCH v2 03/15] kvm: Add arch-specific per-VM debugfs support

Introduce per-VM debugfs for providing per-VM debug information. Signed-off-by: Suravee Suthikulpanit --- arch/mips/kvm/mips.c | 5 + arch/powerpc/kvm/powerpc.c | 5 + arch/s390/kvm/kvm-s390.c | 5 + arch/x86/kvm/debugfs.c | 5 + include/linux/kvm_host.h | 1 + virt

[PATCH v2 07/15] kvm: x86: svm: Add support to activate/deactivate posted interrupts

Introduce interface for activate/deactivate posted interrupts, and implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 4 arch/x86/kvm/svm.c | 44 +

[PATCH v2 10/15] kvm: x86: hyperv: Use APICv deactivate request interface

Since disabling APICv has to be done for all vcpus on AMD-based system, adopt the newly introduced kvm_make_apicv_deactivate_request() intereface. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/hyperv.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch

[PATCH v2 01/15] kvm: x86: Modify kvm_x86_ops.get_enable_apicv() to use struct kvm parameter

Generally, APICv for all vcpus in the VM are enable/disable in the same manner. So, get_enable_apicv() should represent APICv status of the VM instead of each VCPU. Modify kvm_x86_ops.get_enable_apicv() to take struct kvm as parameter instead of struct kvm_vcpu. Signed-off-by: Suravee Suthikulpan

[PATCH v2 00/15] kvm: x86: Support AMD SVM AVIC w/ in-kernel irqchip mode

The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before enabling AVIC")' was introduced to fix miscellaneous boot-hang issues when enable AVIC. This is mainly due to AVIC hardware doest not #vmexit on write to LAPIC EOI register resulting in-kernel PIC and IOAPIC to wait and do not i

Re: [PATCH v3] sched/topology: Improve load balancing on AMD EPYC

Matt, On 7/23/2019 5:48 AM, Matt Fleming wrote: > SD_BALANCE_{FORK,EXEC} and SD_WAKE_AFFINE are stripped in sd_init() > for any sched domains with a NUMA distance greater than 2 hops > (RECLAIM_DISTANCE). The idea being that it's expensive to balance > across domains that far apart. > > However,

Re: [PATCH] sched/topology: Improve load balancing on AMD EPYC

Matt On 6/28/2019 10:15 AM, Matt Fleming wrote: > On Wed, 26 Jun, at 09:18:01PM, Suthikulpanit, Suravee wrote: >> >> We use 16 to designate 1-hop latency (for different node within the same >> socket). >> For across-socket access, since the latency is greater, w

Re: [PATCH 1/6] KVM: x86: Add callback functions for handling APIC ID, DFR and LDR update

Paolo, On 7/3/2019 4:16 PM, Paolo Bonzini wrote: > On 22/03/19 12:57, Suthikulpanit, Suravee wrote: >> Add hooks for handling the case when guest VM update APIC ID, DFR and LDR. >> This is needed during AMD AVIC is temporary deactivated. >> >> Signed-off-by: Suravee

Re: [PATCH 4/6] kvm: lapic: Add apicv activate/deactivate helper function

Jan, On 5/8/2019 5:27 PM, Jan H. Schönherr wrote: > On 22/03/2019 12.57, Suthikulpanit, Suravee wrote: >> Introduce a helper function for setting lapic parameters when >> activate/deactivate apicv. >> >> Signed-off-by: Suravee Suthikulpanit >> -

Re: [PATCH 3/6] svm: Add support for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT setup/destroy

Jan, On 5/8/2019 2:14 PM, Jan H. Schönherr wrote: > On 22/03/2019 12.57, Suthikulpanit, Suravee wrote: >> Activate/deactivate AVIC requires setting/unsetting the memory region used >> for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT. So, re-factor avic_init_access_page() >> to avic_se

Re: [PATCH] sched/topology: Improve load balancing on AMD EPYC

On 6/24/19 9:24 AM, Mel Gorman wrote: > On Wed, Jun 19, 2019 at 10:34:37PM +0100, Matt Fleming wrote: >> On Tue, 18 Jun, at 02:33:18PM, Peter Zijlstra wrote: >>> On Tue, Jun 18, 2019 at 11:43:19AM +0100, Matt Fleming wrote: This works for me under all my tests. Thoughts? --->8--- >>>

Re: [RFC PATCH 8/8] svm: Allow AVIC with in-kernel irqchip mode

Hi, On 6/15/19 9:28 AM, Maxim Levitsky wrote: > On Wed, 2019-02-06 at 11:20 +0000, Suthikulpanit, Suravee wrote: >> Alex, >> >> On 2/6/19 1:34 AM, Alex Williamson wrote: >>> On Mon, 4 Feb 2019 14:42:32 +0000 >>> "Suthikulpanit, Suravee" wrote: >

Re: [PATCH 6/6] svm: Temporary deactivate AVIC during ExtINT handling

Hi Jan, On 5/8/19 12:37 PM, Jan H. Schönherr wrote: > [CAUTION: External Email] > > Hi Suravee. > > I wonder, how this interacts with Hyper-V SynIC; see comments below. > > On 22/03/2019 12.57, Suthikulpanit, Suravee wrote: >> AMD AVIC does not support ExtINT. Theref

[PATCH v2] svm/avic: Allow avic_vcpu_load logic to support host APIC ID 255

Current logic does not allow VCPU to be loaded onto CPU with APIC ID 255. This should be allowed since the host physical APIC ID field in the AVIC Physical APIC table entry is an 8-bit value, and APIC ID 255 is valid in system with x2APIC enabled. Instead, do not allow VCPU load if the host APIC ID

Re: [PATCH] svm/avic: Do not send AVIC doorbell to self

Alex, On 5/7/2019 8:16 AM, Graf, Alexander wrote: > [CAUTION: External Email] > > On 03.05.19 15:38, Suthikulpanit, Suravee wrote: >> AVIC doorbell is used to notify a running vCPU that interrupts >> has been injected into the vCPU AVIC backing page. Current logic >&g

Re: [PATCH] svm/avic: Allow avic_vcpu_load logic to support host APIC ID 255

Alex, Actually, a second thought on this patch, I should have been using AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK ---> On 5/9/19 12:39 PM, Suthikulpanit, Suravee wrote: > [CAUTION: External Email] > > Alex, > > On 5/7/19 9:16 AM, Graf, Alexander wrote: >> [CAUTION:

Re: [PATCH] svm/avic: Allow avic_vcpu_load logic to support host APIC ID 255

Alex, On 5/7/19 9:16 AM, Graf, Alexander wrote: > [CAUTION: External Email] > > On 03.05.19 15:37, Suthikulpanit, Suravee wrote: >> Current logic does not allow VCPU to be loaded onto CPU with >> APIC ID 255. This should be allowed since the host physical APIC ID >>

[PATCH] svm/avic: Allow avic_vcpu_load logic to support host APIC ID 255

Current logic does not allow VCPU to be loaded onto CPU with APIC ID 255. This should be allowed since the host physical APIC ID field in the AVIC Physical APIC table entry is an 8-bit value, and APIC ID 255 is valid in system with x2APIC enabled. Instead, do not allow VCPU load if the host APIC I

[PATCH] svm/avic: Do not send AVIC doorbell to self

AVIC doorbell is used to notify a running vCPU that interrupts has been injected into the vCPU AVIC backing page. Current logic checks only if a VCPU is running before sending a doorbell. However, the doorbell is not necessary if the destination CPU is itself. Add logic to check currently running

Re: [PATCH v2] svm/avic: Fix invalidate logical APIC id entry

Ping On 3/26/19 10:57 AM, Suthikulpanit, Suravee wrote: > Only clear the valid bit when invalidate logical APIC id entry. > The current logic clear the valid bit, but also set the rest of > the bits (including reserved bits) to 1. > > Fixes: 98d90582be2e ('svm: Fix AVIC

Re: [PATCH] Revert "svm: Fix AVIC incomplete IPI emulation"

Ping On 3/20/19 3:12 PM, Suthikulpanit, Suravee wrote: > This reverts commit bb218fbcfaaa3b115d4cd7a43c0ca164f3a96e57. > > As Oren Twaig pointed out the old discussion: > >https://patchwork.kernel.org/patch/8292231/ > > that the change coud potentially cause an ex

Re: [RFC PATCH v2 11/14] x86/watchdog/hardlockup: Add an HPET-based hardlockup detector

Hi Neri, While trying out this patch series, I found that it does not work when the HPET timer is in periodic mode. On 2/27/19 11:05 PM, Ricardo Neri wrote: > .. > diff --git a/arch/x86/kernel/watchdog_hld_hpet.c > b/arch/x86/kernel/watchdog_hld_hpet.c > new file mode 100644 > index 000

[PATCH v2] svm/avic: Fix invalidate logical APIC id entry

Only clear the valid bit when invalidate logical APIC id entry. The current logic clear the valid bit, but also set the rest of the bits (including reserved bits) to 1. Fixes: 98d90582be2e ('svm: Fix AVIC DFR and LDR handling') Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 3 ++-

Re: [PATCH] svm/avic: Fix invalidate logical APIC id entry

On 3/22/19 8:04 PM, Vitaly Kuznetsov wrote: > "Suthikulpanit, Suravee" writes: > >> Only clear the valid bit when invalidate logical APIC id entry. >> The current logic clear the valid bit, but also set the rest of >> the bits (including reserved bits) to

[PATCH 2/6] svm: Add AMD AVIC handlers for APIC ID, DFR and LDR update

During AVIC temporary deactivation, guest could update APIC ID, DFR and LDR registers, which would not be trapped by avic_unaccelerated_ccess_interception(). In this case, we need to update the AVIC logical APIC ID table accordingly. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c |

[PATCH 4/6] kvm: lapic: Add apicv activate/deactivate helper function

Introduce a helper function for setting lapic parameters when activate/deactivate apicv. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/lapic.c | 23 ++- arch/x86/kvm/lapic.h | 1 + 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/lapic.c b

[PATCH 5/6] KVM: x86: Add interface for run-time activate/de-activate APIC virtualization

When activate / deactivate AVIC during runtime, all vcpus has to be operating in the same mode. So, introduce new interface to request all vCPUs to activate/deactivate APICV. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 8 ++ arch/x86/kvm/x86.c | 4

[PATCH 6/6] svm: Temporary deactivate AVIC during ExtINT handling

AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary deactivated and fall back to using legacy interrupt injection via vINTR and interrupt window. Introduce svm_request_activate/deactivate_avic() helper functions, which handle steps required to activate/deactivate AVIC. Signed-off-

[PATCH 0/6] KVM/x86: Add workaround to support ExtINT with AVIC

This series is one of the prerequisites for supporting AMD AVIC with in-kernel irqchip (kernel_irqchip=on). Since AVIC does not support ExtINT interrupt, which is required during the booting phase of Windows and FreeBSD VMs (e.g. PIT -> PIC -> ExtInt). This results in VM hang in the boot loader wi

[PATCH 3/6] svm: Add support for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT setup/destroy

Activate/deactivate AVIC requires setting/unsetting the memory region used for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT. So, re-factor avic_init_access_page() to avic_setup_access_page() and add srcu_read_lock/unlock, which are needed to allow this function to be called during run-time. Also, introduce av

[PATCH 1/6] KVM: x86: Add callback functions for handling APIC ID, DFR and LDR update

Add hooks for handling the case when guest VM update APIC ID, DFR and LDR. This is needed during AMD AVIC is temporary deactivated. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 3 +++ arch/x86/kvm/lapic.c| 6 ++ 2 files changed, 9 insertions(+) diff

[PATCH] svm/avic: Fix invalidate logical APIC id entry

Only clear the valid bit when invalidate logical APIC id entry. The current logic clear the valid bit, but also set the rest of the bits (including reserved bits) to 1. Fixes: 98d90582be2e ('svm: Fix AVIC DFR and LDR handling') Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 2 +-

[PATCH] Revert "svm: Fix AVIC incomplete IPI emulation"

This reverts commit bb218fbcfaaa3b115d4cd7a43c0ca164f3a96e57. As Oren Twaig pointed out the old discussion: https://patchwork.kernel.org/patch/8292231/ that the change coud potentially cause an extra IPI to be sent to the destination vcpu because the AVIC hardware already set the IRR bit befor

Re: [PATCH] svm: Fix AVIC incomplete IPI emulation

Oren On 3/13/19 8:05 PM, Oren Twaig wrote: > Hi Suravee, > > Turns out, the _same_ bug was already discussed in the past by > yourself, Paolo and Radim (both now 'cc'-ed) > > Please read it here: > https://patchwork.kernel.org/patch/8292231/ > > > After reading that thread, I have couple of qu

Re: [PATCH] svm: Fix AVIC incomplete IPI emulation

Oren, On 3/11/19 6:38 PM, Suthikulpanit, Suravee wrote: > However, looking a bit more closely, I notice the logic in > svm_deliver_avic_intr() > should also have been changed from kvm_vcpu_wake_up() to kvm_vcpu_kick() > since the latter will result in clearing the IRR bit for th

Re: [PATCH] svm: Fix AVIC incomplete IPI emulation

Hi Oren, Sorry for delay response. On 3/5/19 1:15 AM, Oren Twaig wrote: > Hello Suravee, > > According to AMD's SDM, the target-not-running incomplete > ipi exit is only received if any of the destination cpus had the > not-running bit set in the avic backing page. I believe you are referring t

Re: [RFC PATCH 8/8] svm: Allow AVIC with in-kernel irqchip mode

Alex, On 2/6/19 1:34 AM, Alex Williamson wrote: > On Mon, 4 Feb 2019 14:42:32 + > "Suthikulpanit, Suravee" wrote: > >> Once the IRQ ack notifier for in-kernel PIT is no longer required >> and run-time AVIC activate/deactivate is supported, we can remove &

Re: [PATCH] svm: Fix improper check when deactivate AVIC

Paolo, On 2/1/19 6:01 PM, Suravee Suthikulpanit wrote: > Paolo, > > On 1/30/19 11:22 PM, Paolo Bonzini wrote: >> On 29/01/19 09:09, Suthikulpanit, Suravee wrote: >>> The function svm_refresh_apicv_exec_ctrl() always returning prematurely >>> as kvm_vcpu_apicv_

[RFC PATCH 8/8] svm: Allow AVIC with in-kernel irqchip mode

Once the IRQ ack notifier for in-kernel PIT is no longer required and run-time AVIC activate/deactivate is supported, we can remove the kernel irqchip split mode requirement for AVIC. Hence, remove the check for irqchip split mode when enabling AVIC. Cc: Radim Krčmář Cc: Paolo Bonzini Signed-of

[RFC PATCH 2/8] KVM: x86: Add interface for run-time activate/de-activate APIC virtualization

Certain types of interrupt cannot be supported by AMD AVIC hardware. Therefore, there is a need to temporary deactivate AVIC and fallback to legacy interrupt injection mechanism. Since AMD AVIC requires all vcpus to be operating in the same mode. So, introduce new interface to request all vCPUs to

[RFC PATCH 7/8] KVM: i8254: Remove need for irq ack notifier

From: Julian Stecklina ACK notifiers don't work with AMD AVIC when the PIT interrupt is delivered as edge-triggered fixed interrupt via the IOAPIC. AMD processors cannot exit on EOI for these interrupts. The ACK notifiers do work when the interrupt is delivered via PIC as ExtINT, because the ACK

[RFC PATCH 6/8] svm: Temporary deactivate AVIC during ExtINT handling

AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary deactivated and fall back to using legacy interrupt injection via vINTR and interrupt window. Introduce svm_request_activate/deactivate_avic() helper functions, which handle steps required to activate/deactivate AVIC. Signed-off-

[RFC PATCH 5/8] svm: Add support for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT setup/destroy

Activate/deactivate AVIC requires setting/unsetting the memory region used for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT. So, re-factor avic_init_access_page() to avic_setup_access_page() and add srcu_read_lock/unlock, which are needed to allow this function to be called during run-time. Also, introduce av

[RFC PATCH 1/8] svm: Fix improper check when deactivate AVIC

The function svm_refresh_apicv_exec_ctrl() always returning prematurely as kvm_vcpu_apicv_active() always return false when calling from the function arch/x86/kvm/x86.c:kvm_vcpu_deactivate_apicv(). This is because the apicv_active is set to false just before calling refresh_apicv_exec_ctrl(). Also

[RFC PATCH 3/8] KVM: x86: Add callback functions for handling APIC ID, DFR and LDR update

Add hooks for handling the case when guest VM update APIC ID, DFR and LDR. This is needed during when AMD AVIC is temporary deactivated. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 3 +++ arch/x86/kvm/lapic.c| 11 +-- 2 files changed, 12 insert

[RFC PATCH 4/8] svm: Add AMD AVIC handlers for APIC ID, DFR and LDR update

During AVIC temporary deactivation, guest could update APIC ID, DFR and LDR registers, which would not be trapped by avic_unaccelerated_ccess_interception(). In this case, we need to update the AVIC logical APIC ID table accordingly. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c |

[RFC PATCH 0/8] KVM: x86: svm: Enabling AVIC with in kernel irqchip

Currently, AMD AVIC can only be enabled when creating VM in irqchip split mode, which is due to the following issues: * AMD AVIC does not support ExtINT, which is required during booting phase of Windows and FreeBSD VMs. This results in hanging in the boot loaders. * Untrap APIC E

Re: [PATCH] svm: Fix improper check when deactivate AVIC

Paolo, On 1/30/19 11:22 PM, Paolo Bonzini wrote: > On 29/01/19 09:09, Suthikulpanit, Suravee wrote: >> The function svm_refresh_apicv_exec_ctrl() always returning prematurely >> as kvm_vcpu_apicv_active() always return false when calling from >> the func

[PATCH] svm: Fix improper check when deactivate AVIC

The function svm_refresh_apicv_exec_ctrl() always returning prematurely as kvm_vcpu_apicv_active() always return false when calling from the function arch/x86/kvm/x86.c:kvm_vcpu_deactivate_apicv(). This is because the apicv_active is set to false just before calling refresh_apicv_exec_ctrl(). Also

[PATCH] svm: Fix AVIC DFR and LDR handling

Current SVM AVIC driver makes two incorrect assumptions: 1. APIC LDR register cannot be zero 2. APIC DFR for all vCPUs must be the same LDR=0 means the local APIC does not support logical destination mode. Therefore, the driver should mark any previously assigned logical APIC ID table entry as

Re: [PATCH v3] iommu: amd: Fix IOMMU page flush when detach device from a domain

Joerg, On 1/24/19 9:11 PM, j...@8bytes.org wrote: > On Thu, Jan 24, 2019 at 04:16:45AM +0000, Suthikulpanit, Suravee wrote: >> drivers/iommu/amd_iommu.c | 15 +++ >> 1 file changed, 11 insertions(+), 4 deletions(-) > > Applied, thanks Suravee. > Thanks

[PATCH v3] iommu: amd: Fix IOMMU page flush when detach device from a domain

From: Suravee Suthikulpanit When a VM is terminated, the VFIO driver detaches all pass-through devices from VFIO domain by clearing domain id and page table root pointer from each device table entry (DTE), and then invalidates the DTE. Then, the VFIO driver unmap pages and invalidate IOMMU pages.

Re: [PATCH] iommu/amd: Fix IOMMU page flush when detach all devices from a domain

Joerg, On 1/23/19 2:56 PM, j...@8bytes.org wrote: > Hi Suravee, > > On Tue, Jan 22, 2019 at 03:53:18PM +, Suthikulpanit, Suravee wrote: >> Thanks for the detail. Alright then, let's just go with the version you >> sent on 1/16/19. Do you want me to resend V3 with

Re: [PATCH] iommu/amd: Fix IOMMU page flush when detach all devices from a domain

Joerg, On 1/22/19 5:44 PM, j...@8bytes.org wrote: > Hi Suravee, > > On Thu, Jan 17, 2019 at 08:44:36AM +, Suthikulpanit, Suravee wrote: >> Then, in __domain_flush_pages, we issue command when the dev_iommu[] >= 0. >> This should preserve previous behavior, and only a

[PATCH] svm: Fix AVIC incomplete IPI emulation

From: Suravee Suthikulpanit In case of incomplete IPI with invalid interrupt type, the current SVM driver does not properly emulate the IPI, and fails to boot FreeBSD guests with multiple vcpus when enabling AVIC. Fix this by update APIC ICR high/low registers, which also emulate sending the IPI

[PATCH] svm: Add warning message for AVIC IPI invalid target

From: Suravee Suthikulpanit Print warning message when IPI target ID is invalid due to one of the following reasons: * In logical mode: cluster > max_cluster (64) * In physical mode: target > max_physical (512) * Address is not present in the physical or logical ID tables Signed-off-by: Su

Re: [PATCH] iommu/amd: Fix IOMMU page flush when detach all devices from a domain

Joerg, On 1/17/19 3:44 PM, Suravee Suthikulpanit wrote: > Joerg, > > On 1/17/19 12:08 AM, j...@8bytes.org wrote: >> On Wed, Jan 16, 2019 at 02:08:55PM +, Suthikulpanit, Suravee wrote: >>> Actually, I am not sure how we would be missing the flush on the last >>

[PATCH v2] iommu/amd: Fix IOMMU page flush when detach all devices from a domain

From: Suravee Suthikulpanit When a VM is terminated, the VFIO driver detaches all pass-through devices from VFIO domain by clearing domain id and page table root pointer from each device table entry (DTE), and then invalidates the DTE. Then, the VFIO driver unmap pages and invalidate IOMMU pages.

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