i/controller/mobiveil' and refactor it according
> to the RC and EP abstraction.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> Reviewed-by: Subrahmanya Lingappa
> ---
> V5:
> - Regenerated this patch on the new base.
> - Retouched t
s not getting loaded.
I belive it should be sufficient to mention in code comment: "Fixing
the class code as hardware is not reflecting the correct class code",
And the changelog for this patch mentioning "avoid changing the
revision ID during the class code fix"
struct mobiveil_pcie;
> +struct mobiveil_pcie_ep;
>
> struct mobiveil_msi { /* MSI information */
> struct mutex lock; /* protect bitmap variable */
> @@ -169,6 +190,29 @@ struct mobiveil_pab_ops {
> int (*host_init)(struct mobiveil_pcie *pcie);
> };
>
> +struct mobiveil_pcie_ep_ops {
> + void (*ep_init)(struct mobiveil_pcie_ep *ep);
> + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
> +enum pci_epc_irq_type type, u16 interrupt_num);
> +};
> +
> +struct mobiveil_pcie_ep {
> + struct pci_epc *epc;
> + struct mobiveil_pcie_ep_ops *ops;
> + phys_addr_t phys_base;
> + size_t addr_size;
> + size_t page_size;
> + phys_addr_t *outbound_addr;
> + unsigned long *ob_window_map;
> + u32 num_ob_windows;
> + void __iomem *msi_mem;
> + phys_addr_t msi_mem_phys;
> + u8 msi_cap; /* MSI capability offset */
> + u8 msix_cap;/* MSI-X capability offset */
> + u8 bar_num;
> + u32 pf_num;
> +};
> +
> struct mobiveil_pcie {
> struct platform_device *pdev;
> struct list_head *resources;
> @@ -181,7 +225,10 @@ struct mobiveil_pcie {
> u32 ib_wins_configured; /* configured inbound windows */
> const struct mobiveil_pab_ops *ops;
> struct root_port rp;
> + struct mobiveil_pcie_ep ep;
> };
> +#define to_mobiveil_pcie_from_ep(endpoint) \
> + container_of((endpoint), struct mobiveil_pcie, ep)
>
> int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
> int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
> @@ -226,4 +273,21 @@ static inline void csr_writeb(struct mobiveil_pcie
> *pcie, u32 val, u32 off)
> csr_write(pcie, val, off, 0x1);
> }
>
> +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
> + int bar, u64 phys);
> +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
> + u64 phys, u64 bus_addr, u8 func, u64 size);
> +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
> +u8 func_no, u8 bar);
> +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
> +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8
> func_no);
> +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
> +u8 interrupt_num);
> +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
> +u16 interrupt_num);
> +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, enum pci_barno
> bar);
> +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
> #endif /* _PCIE_MOBIVEIL_H */
> --
> 1.7.1
>
Please review and fix macro alignments, otherwise looks ok.
Reviewed-by: Subrahmanya Lingappa
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> When LX2 PCIe controller is sending multiple split completions and
> ACK latency expires indicating that ACK should be send at priority.
> But because of large number of split completions and FC update DLLP,
> the con
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> PCIe configuration access to non-existent function triggered
> SERROR interrupt exception.
>
> Workaround:
> Disable error reporting on AXI bus during the Vendor ID read
> transactions in enumeration.
>
> This ERRATA
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No
@ -152,7 +152,7 @@ struct mobiveil_pab_ops {
>
> struct mobiveil_pcie {
> struct platform_device *pdev;
> - struct list_head resources;
> + struct list_head *resources;
> void __iomem *csr_axi_slave_base; /* PAB registers base */
> phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
> void __iomem *apb_csr_base; /* MSI register base */
> @@ -165,6 +165,7 @@ struct mobiveil_pcie {
> };
>
> int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
> +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
> bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
> int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
> void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64
> cpu_addr,
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> + csr_write(pcie, val, off, 0x1);
> +}
> +
> #endif /* _PCIE_MOBIVEIL_H */
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
biveil.c
> @@ -222,7 +222,7 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
> usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> }
>
> - dev_err(&pcie->pdev->dev, "link never came up\n");
> + dev_info(&pcie->pdev->dev, "link never came up\n");
>
> return -ETIMEDOUT;
> }
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
ram_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64
> cpu_addr,
> u64 pci_addr, u32 type, u64 size);
> +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
> +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
> u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
> void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
>
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up. And allow CFG transactions to all functions of
> Endpoint implemented multiple functions.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mo
l/pcie-mobiveil-plat.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ddcdc29dfe1f..3bca9642b08b 100644
> --- a/MAINTAINERS
> ++
r_readl(pcie, PCI_PRIMARY_BUS);
> + value &= 0xff00;
> + value |= 0x00ff0100;
> + csr_writel(pcie, value, PCI_PRIMARY_BUS);
> +
> /*
> * program Bus Master Enable Bit in Command Register in PAB Config
> * Space
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
> is not used in current code, and "apb_csr" is not used by some
> platforms.
>
> Signed
;
> }
>
> @@ -902,6 +900,8 @@ static int mobiveil_pcie_probe(struct platform_device
> *pdev)
> goto error;
> }
>
> + irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
> +
> ret = devm_request_pci_bus_resour
Lorenzo,
On Tue, Feb 5, 2019 at 11:13 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> > Reviewed-by: Subrahmanya Lingappa
>
> I have a feeling you do not read what I write.
My apologies, I do read. I am new to reviewing
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Fix up the Class Code to PCI bridge, do not change the Revision ID.
> And move the fixup to mobiveil_host_init function.
>
> Fixes: 9af6bcb11e12 ("PCI: mobive
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Host initial sequence does not depend on PCIe link up, so move it
> to the place just before the enumeration.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: M
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> In the loop block, there is not code change the loop key,
> this patch updated the loop key by re-read the INTx status
> register.
>
> This patch also change t
ZQ,
please correct the tab spacing of the macro definitions, otherwise its OK.
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Outbound window routine:
> - Removed unused var definition and register read operations.
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The inbound windows have different register set with outbound windows.
> This patch change the MEM inbound window to the first one.
>
> Signed-off-by: Hou Zh
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As the .map_bus() use the WIN_NUM_0 for CFG transactions,
> it's better passing WIN_NUM_0 explicitly when initialize
> the CFG outbound window.
>
>
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As it won't delete any node in this iteration, replaced
> the function resource_list_for_each_entry_safe() with
> the resource_list_for_each_entry().
>
>
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It should get PCI base address from the DT node property 'ranges'
> to setup MEM/IO outbound windows instead of always zero.
>
> Fixes: 9af6bcb11e12 (&q
Zhiqiang,
why are we removing multi-MSI support ?
what functionality this driver is not providing to support it ?
Thanks.
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The current code does not support multiple MSIs, so remove
> the corresponding flag from the msi_d
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This patch corrected the returned error number by convention,
> and removed a unnecessary error check.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan L
Zhiqiang,
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Just format the code without functionality change.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 261 +---
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It's confused that R/W some registers by csr_readl()/csr_writel(),
> while others by read_paged_register()/write_paged_register().
> Actually the low 3KB of 4
Lorenzo,
My apologies again,
I have started looking into these.
Thanks,
On Mon, Feb 4, 2019 at 9:43 PM Lorenzo Pieralisi
wrote:
>
> On Mon, Feb 04, 2019 at 07:44:25PM +0530, Subrahmanya Lingappa wrote:
> >Bjorn,
> >My apologies, I was away for a while from this
Lorenzo,
You are right, I reviewed few DT files, will need some time to review
this train.
I will start doing it in a while.
Thanks for pitching in.
Thanks.
On Mon, Dec 3, 2018 at 8:58 AM Lorenzo Pieralisi
wrote:
>
> On Tue, Nov 06, 2018 at 01:19:03PM +, Z.q. Hou wrote:
> > From: Hou Zhiqia
Acked-by: Subrahmanya Lingappa
On Tue, Nov 6, 2018 at 6:50 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
> is not used in current code, and "apb_csr" is not u
onsidered deprecated for
> FDT though we've still been requiring it for PCI hosts as it is useful
> for finding PCI buses.
>
> Cc: Will Deacon
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Alan Douglas
> Cc: Subrahmanya Lingappa
> Cc: Michal Simek
> Cc: l
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit d3743012230f8dab30d47caba1f2ee9e382385e7 ]
>
> PCI mobiveil host controller driver currently fails to compile
> with the following e
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit af3f606e0bbb6d811c50b7b90fe324b07fb7cab8 ]
>
> The field pcie_reg_base in struct mobiveil_pcie represents a physical
> addre
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