7;s review comments
- pcie_print_link_status is used to print Link information.
- Added IARR1/IMAP1 window map definition.
Bharat Gooty (1):
PCI: iproc: Fix out-of-bound array accesses
Roman Bacik (1):
PCI: iproc: Invalidate correct PAXB inbound windows
Srinath Mannam (1):
PCI: ipro
After successful linkup more comprehensive information about PCIe link
speed and link width will be displayed to the console.
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/pcie-iproc.c
b
From: Bharat Gooty
Declare the full size array for all revisions of PAX register sets
to avoid potentially out of bound access of the register array
when they are being initialized in iproc_pcie_rev_init().
Fixes: 06324ede76cdf ("PCI: iproc: Improve core register population")
Signed-off-by: Bhar
/IMAP1
because it was missed in previous patch.
Fixes: 9415743e4c8a ("PCI: iproc: Invalidate PAXB address mapping")
Signed-off-by: Roman Bacik
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
di
On Thu, Sep 17, 2020 at 7:22 AM Rob Herring wrote:
>
Hi Rob,
Thanks for review.
> On Tue, Sep 15, 2020 at 07:15:41PM +0530, Srinath Mannam wrote:
> > After successful linkup more comprehensive information about PCIe link
> > speed and link width will be displayed to the conso
On Thu, Sep 17, 2020 at 3:38 AM Bjorn Helgaas wrote:
>
Hi Bjorn,
Thanks for review.
> On Tue, Sep 15, 2020 at 07:15:38PM +0530, Srinath Mannam wrote:
> > This patch series contains fixes and improvements to pcie iproc driver.
> >
> > This patch set is based on Linux-5.
harat Gooty (1):
PCI: iproc: fix out of bound array access
Roman Bacik (1):
PCI: iproc: fix invalidating PAXB address mapping
Srinath Mannam (1):
PCI: iproc: Display PCIe Link information
drivers/pci/controller/pcie-iproc.c | 29 ++---
1 file changed, 22 insertions(
After successful linkup more comprehensive information about PCIe link
speed and link width will be displayed to the console.
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/pcie-iproc.c
b
From: Bharat Gooty
Declare the full size array for all revisions of PAX register sets
to avoid potentially out of bound access of the register array
when they are being initialized in the 'iproc_pcie_rev_init'
function.
Fixes: 06324ede76cdf ("PCI: iproc: Improve core register population")
Signed
/IMAP1
because it was missed in previous patch.
Fixes: 9415743e4c8a ("PCI: iproc: Invalidate PAXB address mapping")
Signed-off-by: Roman Bacik
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
di
Fix IOVA reserve failure in the case when address of first memory region
listed in dma-ranges is equal to 0x0.
Fixes: aadad097cd46f ("iommu/dma: Reserve IOVA for PCIe inaccessible DMA
address")
Signed-off-by: Srinath Mannam
---
Changes from v2:
Modify error message with useful i
On Fri, Sep 11, 2020 at 8:47 PM Bjorn Helgaas wrote:
>
Hi Bjorn,
Thanks for review.
> On Fri, Sep 11, 2020 at 03:55:34PM +0530, Srinath Mannam wrote:
> > Fix IOVA reserve failure in the case when address of first memory region
> > listed in dma-ranges is equal to 0x0.
> >
Fix IOVA reserve failure in the case when address of first memory region
listed in dma-ranges is equal to 0x0.
Fixes: aadad097cd46f ("iommu/dma: Reserve IOVA for PCIe inaccessible DMA
address")
Signed-off-by: Srinath Mannam
---
Changes from v1:
Removed unnecessary changes based
On Wed, Sep 9, 2020 at 5:35 PM Robin Murphy wrote:
>
Hi Robin,
Thanks for review
> On 2020-09-09 06:32, Srinath Mannam wrote:
> > Fix IOVA reserve failure for memory regions listed in dma-ranges in the
> > following cases.
> >
> > - start address of memory region
dress")
Signed-off-by: Srinath Mannam
---
drivers/iommu/dma-iommu.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 5141d49a046b..0a3f67a4f9ae 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers
On Wed, May 27, 2020 at 11:00 PM Robin Murphy wrote:
>
Thanks Robin for your quick response.
> On 2020-05-27 17:03, Srinath Mannam wrote:
> > This patch gives the provision to change default value of MSI IOVA base
> > to platform's suitable IOVA using module parameter. Th
MA address"), inaccessible IOVA address ranges parsed from dma-ranges
property are reserved.
If any platform has the limitaion to access default MSI IOVA, then it can
be changed using "arm-smmu.msi_iova_base=0xa000" command line argument.
Signed-off-by: Srinath Mannam
---
dri
Hi Linus,
We have tested patch with your changes, it works fine.
Thanks a lot for all the help.
Regards,
Srinath.
On Wed, Sep 11, 2019 at 3:13 PM Linus Walleij wrote:
>
> On Thu, Aug 29, 2019 at 5:52 AM Srinath Mannam
> wrote:
>
> > From: Rayagonda Kokatanur
> >
>
9:45AM +0530, Srinath Mannam wrote:
> > From: Abhinav Ratna
> >
> > IPROC PAXB RC doesn't support ACS capabilities and control registers.
> > Add quirk to have separate IOMMU groups for all EPs and functions connected
> > to root port, by masking RR/CR/S
Hi Mathias,
Could you please help to review this patch series?
Regards,
Srinath.
On Wed, Jul 31, 2019 at 3:50 PM Srinath Mannam
wrote:
>
> This patch set adds a quirk in xHCI driver to reset PHY of xHCI port on
> its disconnect event.
>
> This patch set is based on Linux-5.2-r
From: Rayagonda Kokatanur
When multiple instance of iproc-gpio chips are present, a fix up
message[1] is printed during the probe of second and later instances.
This issue is because driver sharing same irq_chip data structure
among multiple instances of driver.
Fix this by allocating irq_chip
From: Li Jin
Fix drive strength for AON/CRMU controller; fix pull-up/down setting
for CCM/CDRU controller.
Fixes: 616043d58a89 ("pinctrl: Rename gpio driver from cygnus to iproc")
Signed-off-by: Li Jin
---
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 96 +---
1 file c
This patch series adds the following fixes to the iProc GPIO driver
- Fix Warning message given for shared irqchip data structure
- Fix pinconfig of pull-up/down and drive strength for AON/CRMU GPIOs
This patch set is based on Linux-5.2-rc4.
Changes from v1:
- Add Fixes tags in both patches
From: Ray Jui
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 28
1 file changed, 24
From: Ray Jui
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
arch/arm/boot/dts/bcm-hr2.dtsi | 30 ++
1 file changed, 26 insertions(+), 4
register
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 100 +++-
drivers/pci/controller/pcie-iproc.h | 6 +++
2 files changed, 104 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c
b
From: Ray Jui
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
arch/arm/boot/dts/bcm-nsp.dtsi | 45 --
1 file changed, 39
This patch series adds PCIe legacy interrupt (INTx) support to the iProc
PCIe driver by modeling it with its own IRQ domain. All 4 interrupts INTA,
INTB, INTC, INTD share the same interrupt line connected to the GIC
in the system. This is now modeled by using its own IRQ domain.
Also update all re
From: Ray Jui
Update the iProc PCIe binding document for better modeling of the legacy
interrupt (INTx) support
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
.../devicetree/bindings/pci/brcm,iproc-pcie.txt| 48 ++
1 file changed, 41 insertions(+), 7
From: Ray Jui
Change the PCIe INTx mapping to model the 4 INTx interrupts in the
IRQ domain of the iProc PCIe controller itself
Signed-off-by: Ray Jui
Signed-off-by: Srinath Mannam
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 30 ++
1 file changed, 26 insertions(+), 4
03:49:52PM +0530, Srinath Mannam wrote:
> > Increase #phy-cells from 1 to 2 to have bitmask of PHY enabled ports.
>
> And from 0 to 1...
>
> Are you going to update all the dts files so when we convert this to
> schema we don't get a bunch of warnings? (Feel free
From: Abhinav Ratna
IPROC PAXB RC doesn't support ACS capabilities and control registers.
Add quirk to have separate IOMMU groups for all EPs and functions connected
to root port, by masking RR/CR/SV/UF bits.
Signed-off-by: Abhinav Ratna
Signed-off-by: Srinath Mannam
---
drivers/pci/qui
renzo Pieralisi wrote:
> > > > On Fri, Apr 12, 2019 at 08:43:32AM +0530, Srinath Mannam wrote:
> > > > > Few SOCs have limitation that their PCIe host can't allow few inbound
> > > > > address ranges. Allowed inbound address ranges are listed in
&g
Unlike DT framework, thermal-zones and its parameters can't be parsed
using ACPI framework. So that ACPI support is removed in this driver.
Signed-off-by: Srinath Mannam
Reported-by: David Woodhouse
---
drivers/thermal/broadcom/sr-thermal.c | 8
1 file changed, 8 deletions(-)
Hi David,
Thank you for notifying..
Hi Sudeep,
I will send a patch to remove ACPI support.
Regards,
Srinath.
On Mon, Apr 29, 2019 at 8:54 PM Sudeep Holla wrote:
>
> On Mon, Apr 29, 2019 at 06:07:12PM +0300, David Woodhouse wrote:
> > On Mon, 2018-05-28 at 11:11 +0530, Srinath
iProc config read flag has to enable for PAXBv2 instead of PAXB.
Fixes: f78e60a29d4ff ("PCI: iproc: Reject unconfigured physical functions from
PAXC")
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
list.
This method is similar to PCI IO resources address ranges reserving in
IOMMU for each EP connected to host bridge.
Signed-off-by: Srinath Mannam
Based-on-patch-by: Oza Pawandeep
Reviewed-by: Oza Pawandeep
---
drivers/iommu/dma-iommu.c | 19 +++
1 file changed, 19 insertions
anges from v3:
- Addressed Robin Murphy review comments.
- pcie-iproc: parse dma-ranges and make sorted resource list.
- dma-iommu: process list and reserve gaps between entries
Changes from v2:
- Patch set rebased to Linux-5.0-rc2
Changes from v1:
- Addressed Oza review comments.
Sr
have detailed
description of feature and implementation.
Thank again for you patience.
Regards,
Srinath.
On Wed, Apr 3, 2019 at 5:01 PM Lorenzo Pieralisi
wrote:
>
> On Wed, Apr 03, 2019 at 08:41:44AM +0530, Srinath Mannam wrote:
> > Hi Lorenzo,
> >
> > Please see my rep
Hi Lorenzo,
Please see my reply below,
On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
>
> [...]
>
> > > Ok - I start to understand. What does it mean in HW terms that your
> > > 32bi
Hi Lorenzo,
Please see my reply below,
On Tue, Apr 2, 2019 at 3:56 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Apr 02, 2019 at 03:20:21PM +0530, Srinath Mannam wrote:
> > Hi Ray,
> >
> > Thanks for detailed explanation.
> > Please see some more details below.
> >
ction. I hope that will help to
> make it more clear.
>
> On 4/1/2019 9:44 AM, Lorenzo Pieralisi wrote:
> > On Mon, Apr 01, 2019 at 11:04:48AM +0530, Srinath Mannam wrote:
> >> Hi Lorenzo,
> >>
> >> Please see my reply below,
> >>
> >> On Fri,
Hi Lorenzo,
Please see my reply below,
On Fri, Mar 29, 2019 at 11:06 PM Lorenzo Pieralisi
wrote:
>
> On Fri, Mar 01, 2019 at 10:22:16AM +0530, Srinath Mannam wrote:
> > In the present driver outbound window configuration is done to map above
> > 32-bit address I/O regions with
Hi Stephen,
Thanks for the notice.
I sent patch to fix this warning.
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1964942.html
Regards,
Srinath.
On Thu, Mar 28, 2019 at 5:59 AM Stephen Rothwell wrote:
>
> Hi Kishon,
>
> After merging the phy-next tree, today's linux-next build
Hi Lorenzo,
Thanks for feedback, I will talk to our HW engineer.
Regards,
Srinath.
On Wed, Mar 27, 2019 at 6:01 PM Lorenzo Pieralisi
wrote:
>
> On Wed, Mar 27, 2019 at 02:08:46PM +0530, Srinath Mannam wrote:
> > Hi Lorenzo/Bjorn,
> >
> > Could you please help to revie
sb: Add Stingray USB PHY driver)
Reported-by: kbuild test robot
Signed-off-by: Srinath Mannam
---
drivers/phy/broadcom/phy-bcm-sr-usb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/broadcom/phy-bcm-sr-usb.c
b/drivers/phy/broadcom/phy-bcm-sr-usb.c
index bfe
Hi Lorenzo/Bjorn,
Could you please help to review this patch series when you have time?
I believe I have addressed all your review comments.
Thanks,
Srinath.
On Fri, Mar 1, 2019 at 10:22 AM Srinath Mannam
wrote:
>
> This patch set extends support of new IPROC PCIe host controller fe
tch series,
> >>
> >> Acked-by: Scott Branden
> >>
> >
> > Kishon, can you let me know when you apply patches 1 and 2 so I can
> > queue up patch 3 for inclusion the 5.2 ARM SoC pull request? Thanks!
>
> merged the dt-binding and sr-usb driver, thanks.
Thanks a
USB PHY driver supports two types of stingray USB PHYs
- Type 1 is a combo PHY contains two PHYs, one SS and one HS.
- Type 2 is a single HS PHY.
These two PHY versons support both Generic xHCI host controller driver
and BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
use SS-PHY in SS mode and HS-PHY in HS mode.
xHCI0 port1 is SS-PHY0, port2 is HS-PHY0.
xHCI1 port1 is SS-PHY1, port2 is HS-PHY2 and port3 is HS-PHY1.
Signed-off-by: Srinath Mannam
---
.../boot/dts/broadcom/stingray/stingray-usb.dtsi | 72 ++
.../arm64/boot/dts/broadcom
- Updated patchset to Linux-5.0-rc2
Changes from v1:
- Addressed Kishon review comments
- phy init call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add Stingray USB PHY binding document
phy: sr-usb: Add Stingray USB PHY driver
arm64: dts: Add USB DT nodes for Stingray SoC
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
Reviewed-by: Rob Herring
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/brcm,stingray-usb
use SS-PHY in SS mode and HS-PHY in HS mode.
xHCI0 port1 is SS-PHY0, port2 is HS-PHY0.
xHCI1 port1 is SS-PHY1, port2 is HS-PHY2 and port3 is HS-PHY1.
Signed-off-by: Srinath Mannam
---
.../boot/dts/broadcom/stingray/stingray-usb.dtsi | 78 ++
.../arm64/boot/dts/broadcom
USB PHY driver supports two types of stingray USB PHYs
- Type 1 is a combo PHY contains two PHYs, one SS and one HS.
- Type 2 is a single HS PHY.
These two PHY versons support both Generic xHCI host controller driver
and BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
comments
- phy init call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add Stingray USB PHY binding document
phy: sr-usb: Add Stingray USB PHY driver
arm64: dts: Add USB DT nodes for Stingray SoC
.../bindings/phy/brcm,stingray-usb-phy.txt | 40 +++
.../boot/dts
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/brcm,stingray-usb-phy.txt
diff --git a
Hi Rob,
Thank you, I will send next patch set with the changes as you suggested.
Regards,
Srinath.
On Tue, Mar 12, 2019 at 3:00 AM Rob Herring wrote:
>
> On Sun, Mar 10, 2019 at 10:32 PM Srinath Mannam
> wrote:
> >
> > Hi Rob,
> >
> > Please find my comments be
Hi Rob,
Please find my comments below,
On Sat, Feb 23, 2019 at 1:05 AM Rob Herring wrote:
>
> On Fri, Feb 22, 2019 at 11:29 AM Srinath Mannam
> wrote:
> >
> > Hi Rob,
> >
> > Thanks for the review, Please find my comments below in line.
> >
> >
ranges = <0x8300 0x0 0x4200 0x0 0x4200 0 0x200>;
I/O region address is 0x4200
Signed-off-by: Srinath Mannam
Signed-off-by: Abhishek Shah
Signed-off-by: Ray Jui
---
drivers/pci/controller/pcie-iproc.c | 21 +++--
1 file changed, 19 insertions(+),
.
Changes from v2:
- Based on Lorenzo Pieralisi comments, commit logs are expanded.
Changes from v1:
- Addressed Bjorn Helgaas comments.
- Removed set order mode patch from patchset.
Srinath Mannam (2):
PCI: iproc: Add CRS check in config read
PCI: iproc: Add outbound configuration for
using status flags before reissue config read.
Signed-off-by: Srinath Mannam
---
drivers/pci/controller/pcie-iproc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c
b/drivers/pci/controller/pcie-iproc.c
index
Hi Lorenzo,
Thanks for the review.. Please see my comments below in line..
Regards,
Srinath.
On Thu, Feb 28, 2019 at 9:43 PM Lorenzo Pieralisi
wrote:
>
> On Wed, Feb 20, 2019 at 10:03:55PM +0530, Srinath Mannam wrote:
> > In the present driver outbound window configuration is done
Hi Rob,
Thanks for the information. Please find my comments below.
Regards,
Srinath.
On Tue, Feb 26, 2019 at 11:33 PM Rob Herring wrote:
>
> On Mon, Feb 25, 2019 at 10:57 PM Srinath Mannam
> wrote:
> >
> > Hi Rob,
> > Thanks for the review, Please see my comments bel
Hi Rob,
Thanks for the review, Please see my comments below in line.
Regards,
Srinath.
On Tue, Feb 26, 2019 at 3:08 AM Rob Herring wrote:
>
> On Tue, Feb 05, 2019 at 11:48:53AM +0530, Srinath Mannam wrote:
> > Add usb-phy-port-reset optional property to set quirk in xhci platfor
Hi Rob,
Thanks for the review, Please find my comments below in line.
On Fri, Feb 22, 2019 at 10:50 PM Rob Herring wrote:
>
> On Wed, Feb 20, 2019 at 04:04:00PM +0530, Srinath Mannam wrote:
> > Add DT binding document for Stingray USB PHY.
> >
> > Signed-off-by: Srinath
Hi Bjorn,
Please help to review this patch series.
Thank you.
Regards,
Srinath.
On Fri, Jan 25, 2019 at 3:44 PM Srinath Mannam
wrote:
>
> Few SOCs have limitation that their PCIe host can't allow few inbound
> address ranges. Allowed inbound address ranges are listed in dma-ranges
ranges = <0x8300 0x0 0x4200 0x0 0x4200 0 0x200>;
I/O region address is 0x4200
Signed-off-by: Srinath Mannam
Signed-off-by: Abhishek Shah
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
Reviewed-by: Vikram Prakash
---
drivers/pci/controller/pcie-
using status flags before reissue config read.
Signed-off-by: Srinath Mannam
Reviewed-by: Ray Jui
---
drivers/pci/controller/pcie-iproc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c
b/drivers/pci/controller
, commit logs are expanded.
Changes from v1:
- Addressed Bjorn Helgaas comments.
- Removed set order mode patch from patchset.
Srinath Mannam (2):
PCI: iproc: Add CRS check in config read
PCI: iproc: Add outbound configuration for 32-bit I/O region
drivers/pci/controller/pcie-iproc.c | 44
from v2:
- Addressed Kishon review comments
- Updated patchset to Linux-5.0-rc2
Changes from v1:
- Addressed Kishon review comments
- phy init call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add Stingray USB PHY binding document
phy: sr-usb: Add Stingray USB PHY driver
use SS-PHY in SS mode and HS-PHY in HS mode.
xHCI0 port1 is SS-PHY0, port2 is HS-PHY0.
xHCI1 port1 is SS-PHY1, port2 is HS-PHY2 and port3 is HS-PHY1.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../boot/dts/broadcom/stingray/stingray-usb.dtsi | 95
USB PHY driver supports two versions of stingray USB PHYs
- Version 1 is a combo PHY contains one SS and one HS PHYs.
- Version 2 is a single HS PHY.
These two PHY versons support both Generic xHCI host controller driver
and BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
Hi Rob,
Thanks for review, please see my comments below inline.
On Mon, Feb 18, 2019 at 10:52 PM Rob Herring wrote:
>
> On Wed, Feb 06, 2019 at 11:02:25PM +0530, Srinath Mannam wrote:
> > Add DT binding document for Stingray USB PHY.
> >
> > Signed-off-by: Srinath
Hi Kishon,
Could you please help to review and provide your comments to this
patch series when you have time?
Regards,
Srinath.
On Wed, Feb 6, 2019 at 11:03 PM Srinath Mannam
wrote:
>
> These patches add Stingray USB PHY driver and its corresponding
> DT nodes with documentation.
> The following tag should be added to the binding document patch:
> >
> > Reviewed-by: Rob Herring
> >
> > Thanks,
> >
> > Ray
> >
> > On 1/3/2019 12:55 AM, Srinath Mannam wrote:
> > > These patches adds the stingray thermal driver a
Hi Lorenzo,
Thanks for review, please see my comments below inline.
On Wed, Feb 13, 2019 at 12:07 AM Lorenzo Pieralisi
wrote:
>
> On Tue, Feb 05, 2019 at 10:27:01AM +0530, Srinath Mannam wrote:
> > Add configuration to support IPROC PCIe host controller outbound memory
> > w
Hi Lorenzo,
Thanks for review, please see my comments below inline.
On Tue, Feb 12, 2019 at 11:42 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Feb 05, 2019 at 10:27:00AM +0530, Srinath Mannam wrote:
> > In the current implementation, config read output data 0x0001 is
> &
Hi Mathias,
Thanks for comments, Please find my comments below inline.
On Fri, Feb 8, 2019 at 6:00 PM Mathias Nyman
wrote:
>
> On 07.02.2019 17:17, Srinath Mannam wrote:
> > Hi Mathias,
> >
> > Thanks for review, please see my comments below inline.
> >
>
Hi Mathias,
Thanks for review, please see my comments below inline.
On Thu, Feb 7, 2019 at 8:32 PM Mathias Nyman
wrote:
>
> On 05.02.2019 08:18, Srinath Mannam wrote:
> > Add a quirk to reset xHCI port PHY on port disconnect event.
> > Stingray USB HS PHY has an issue, t
USB PHY driver supports all versions of stingray SS and HS USB PHYs.
- Version 1 is a combo PHY contains both SS and HS PHYs.
- Version 2 is a single HS PHY.
These PHYs support both Generic xHCI host controller driver and BDC
Broadcom device controller driver.
Signed-off-by: Srinath Mannam
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add Stingray USB PHY binding document
phy: sr-usb: Add Stingray USB PHY driver
arm64: dts: Add USB DT nodes for Stingray SoC
.../bindings/phy/brcm,stingray-usb-phy.txt | 62
.../boot/dts/broadcom/stingray/stingray
]
| | | |
--- ---
| | | | |
[SS-PHY0] [HS-PHY0][SS-PHY1] [HS-PHY2] [HS-PHY1]
[SS-PHY0/HS-PHY0] and [SS-PHY1/HS-PHY1] are combo PHYs of
version1 category has both SS and HS PHYs..
[HS-PHY2] is HS PHY of version2 category.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian
]
| | | |
--- ---
| | | | |
[SS-PHY0] [HS-PHY0][SS-PHY1] [HS-PHY2] [HS-PHY1]
[SS-PHY0/HS-PHY0] and [SS-PHY1/HS-PHY1] are combo PHYs of
version1 category has both SS and HS PHYs..
[HS-PHY2] is HS PHY of version2 category.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian
call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add Stingray USB PHY binding document
phy: sr-usb: Add Stingray USB PHY driver
arm64: dts: Add USB DT nodes for Stingray SoC
.../bindings/phy/brcm,stingray-usb-phy.txt | 62
.../boot/dts/broadcom/stingray/stingray
USB PHY driver supports all versions of stingray SS and HS USB PHYs.
- Version 1 is a combo PHY contains both SS and HS PHYs.
- Version 2 is a single HS PHY.
These PHYs support both Generic xHCI host controller driver and BDC
Broadcom device controller driver.
Signed-off-by: Srinath Mannam
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
Add a quirk to reset xHCI port PHY on port disconnect event.
Stingray USB HS PHY has an issue, that USB High Speed device detected
at Full Speed after the same port has connected to Full speed device.
This problem can be resolved with that port PHY reset on disconnect.
Signed-off-by: Srinath
Add usb-phy-port-reset optional property to set quirk in xhci platform
driver which forces USB port PHY reset on port disconnect event.
Signed-off-by: Srinath Mannam
Reviewed-by: Ray Jui
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a
This patch set adds a quirk in xHCI driver to reset PHY of xHCI port
on its disconnect event.
This patch set is based on Linux-5.0-rc2.
Srinath Mannam (2):
dt-bindings: usb-xhci: Add usb-phy-port-reset property
drivers: xhci: Add quirk to reset xHCI port PHY
Documentation/devicetree
Add configuration to support IPROC PCIe host controller outbound memory
window mapping with SOC address range inside 4GB boundary, which is 32 bit
AXI address.
Signed-off-by: Srinath Mannam
Signed-off-by: Abhishek Shah
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
Reviewed-by: Vikram
order mode patch from patchset.
Srinath Mannam (2):
PCI: iproc: Add CRS check in config read
PCI: iproc: Add PCIe 32bit outbound memory configuration
drivers/pci/controller/pcie-iproc.c | 44 +
1 file changed, 40 insertions(+), 4 deletions(-)
--
2.7.4
using status flags before reissue config read.
Signed-off-by: Srinath Mannam
Reviewed-by: Ray Jui
---
drivers/pci/controller/pcie-iproc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c
b/drivers/pci/controller
set order mode patch from patchset.
Srinath Mannam (2):
PCI: iproc: Add CRS state check in config read
PCI: iproc: Add PCIe 32bit outbound memory configuration
drivers/pci/controller/pcie-iproc.c | 44 +
1 file changed, 40 insertions(+), 4 deletions
.
Signed-off-by: Srinath Mannam
Based-on-patch-by: Oza Pawandeep
Reviewed-by: Oza Pawandeep
---
drivers/iommu/dma-iommu.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index d19f3d6..81b591b 100644
--- a/drivers/iommu/dma-iommu.c
0-rc2
Changes from v1:
- Addressed Oza review comments.
Srinath Mannam (3):
PCI: Add dma-resv window list
iommu/dma: Reserve IOVA for PCI host reserve address list
PCI: iproc: Add dma reserve resources to host
drivers/iommu/dma-iommu.c | 8 ++
drivers/pci/controller/pcie-ip
dress ranges will be add to this list to avoid IOMMU mapping.
While initializing IOMMU domain of PCI EPs connected to that host bridge
IOVAs for this given list of address ranges will be reserved.
Signed-off-by: Srinath Mannam
Based-on-patch-by: Oza Pawandeep
Reviewed-by: Oza Pawandeep
---
dr
00,
0x1 - 0x8,
0x10 - 0x80 and
0x100 - 0x.
are not allowed to use as inbound addresses.
So that we need to add these address ranges to dma_resv list to reserve
corresponding IOVA address ranges.
Signed-off-by: Srinath Mannam
Based-on-pa
Hi Bjorn,
Thank you, Please see my comments below inline.
On Fri, Jan 25, 2019 at 1:01 AM Bjorn Helgaas wrote:
>
> On Thu, Jan 24, 2019 at 02:10:18PM +0530, Srinath Mannam wrote:
> > On Fri, Jan 18, 2019 at 8:37 PM Bjorn Helgaas wrote:
> > > On Fri, Jan 18, 2019 at 09:5
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