Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it. To match the
> sequence of events, t
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
wrote:
> Hi,
>
> On Wed, Nov 12, 2014 at 12:47 AM, wrote:
>> From: Suravee Suthikulpanit
>>
>> This patch introduces a new DT binding, msi-parent, which can
>> be used to specify MSI-parent phandle for
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, wrote:
> From: Suravee Suthikulpanit
>
> This patch introduces a new DT binding, msi-parent, which can
> be used to specify MSI-parent phandle for a particular PCI
> generic host controller.
>
> Also, it implements and registers set_msi_parent callback.
>
>
Hi Quentin,
On Fri, Nov 7, 2014 at 1:36 PM, Quentin Lambert
wrote:
> Simplify a trivial if-return sequence. Possibly combine with a
> preceding function call.
> Generated by: scripts/coccinelle/misc/simple_return.cocci
>
> Signed-off-by: Quentin Lambert
> ---
>
> Changes in v2:
> - remove a ch
Hi Mark,
Thanks for reviewing patch.
I should have made a note that the binding patch is applied. I will
make a note of this and add to next versions.
Thanks
Srikanth
On Wed, Oct 15, 2014 at 6:15 PM, Mark Rutland wrote:
> Hi,
>
> On Wed, Oct 15, 2014 at 01:00:36PM +0100, Srikant
: Srikanth Thokala
---
Changes in v4:
- Add direction field to VDMA descriptor structure and removed from
channel structure to avoid duplication.
- Check for DMA idle condition before changing the configuration.
- Residue is being calculated in complete_descriptor() and is reported
to slave driver
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul wrote:
> On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
>> > On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
> On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> Apologies for the delay.
>>
>> On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
>> > On Mon, Jul 28,
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas wrote:
> On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> Acked-by: Arnd Bergmann
>
> App
Hi Bjorn,
I fixed the mentioned issues with build-bot in v7. Could you please
take this patch?
Thanks
Srikanth
On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> Acked-by: A
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
> On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> +struct xilinx_dma_chan {
>> + struct xilinx_dma_device *xdev;
>> + u32 ctrl_offset;
>> + spinl
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So
Hi Bjorn,
On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas wrote:
> On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
>> Hi Michal,
>>
>> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
>> > Hi Bjorn,
>> >
>> > On 07/30/2014
Hi Varka Bhadram,
On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram wrote:
> On 08/05/2014 05:09 PM, Srikanth Thokala wrote:
>>
>> Device-tree binding documentation of Xilinx Central DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v2:
&g
Hi Michal,
On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
> Hi Bjorn,
>
> On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
>> Hi Arnd,
>>
>> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
>>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrot
Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xi
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.1
Hi,
Kindly review this patch and please provide your inputs.
Thanks
Srikanth
On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memo
Hi Arnd,
On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>> Hi Arnd and Rob,
>>
>> I discussed with Bjorn and we believe this patch is in good shape to
>> apply. And Bjorn requires ACKs to apply this pa
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote:
>> Device-tree binding documentation of Xilinx DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>
> Looks ok to me,
>
> Acked-by: Arnd Bergmann
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala wrote
: Srikanth Thokala
---
Changes in v3:
- Rebased on 3.16-rc7
Changes in v2:
- Simplified the logic to set SOP and APP words in prep_slave_sg().
- Corrected function description comments to match the return type.
- Fixed some minor comments as suggested by Andy, Thanks.
---
drivers/dma/Kconfig
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xi
Hi Andreas,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Friday, July 25, 2014 3:10 PM
> To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
> Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicet.
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up
Hi Bjorn,
On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas wrote:
> On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Wednesday, May 21, 2014 1:23 PM
> To: Srikanth Thokala
> Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org
> Subject: Re:
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann wrote:
> On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
>> +
>> + if (cfg->ops->is_valid_cfg_access) {
>> + if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
>> +
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala
---
This patch is created with reference from Will's patch series:
1/3 - "ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM"
2/3 - "PCI:
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann wrote:
> On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
>> On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
>> > On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> >> +/**
>> >> + * xilin
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
> On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas wrote:
> On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v3:
>> - Rebase
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Acked-by: Jassi Brar
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and w
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
Acked-by: Rob Herring
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> ---
> Changes in v3:
> -
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul wrote:
> On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory acce
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul wrote:
> On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
>> On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
>> > On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> >> This is the d
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
> On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet wrote:
> On Mon, 7 Apr 2014 20:22:54 +0530
> Srikanth Thokala wrote:
>
>> Kindly review this driver and please let me know if you have any comments.
>
> Here's some comments from a quick look at the patch;
Hi,
Kindly review this driver and please let me know if you have any comments.
Thanks
Srikanth
On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Central Direct Memory Access (AXI
> CDMA) core, which is a soft Xilinx IP core that provides high-ban
Hi,
Kindly review this driver patch and please let me know if you have any comments.
Srikanth
On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwid
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx
: Srikanth Thokala
---
Note:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
Changes in v2:
- Simplified the logi
Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
wrote:
> On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory acce
: Srikanth Thokala
---
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
---
drivers/dma/Kconfig |
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Acked-by: Jassi Brar
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and w
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly
h non-contiguous memory' as
suggested by Jaswinder, Thanks.
Changes in v3:
- Created a separate patch for the DT binding documentation as suggested by
Vinod, Thanks.
- Added support for interleaved frames with non-contiguous memory as suggested
by Lars, Thanks.
- Rebased on v3.14.0-rc2
On Mon, Mar 24, 2014 at 8:53 PM, Jassi Brar wrote:
> On Mon, Mar 24, 2014 at 8:44 PM, Srikanth Thokala wrote:
>> On Mon, Mar 24, 2014 at 4:21 PM, Jassi Brar
>> wrote:
>>> On 24 March 2014 14:30, Srikanth Thokala wrote:
>>>> Hi Jassi,
>>>>
>&g
On Mon, Mar 24, 2014 at 4:21 PM, Jassi Brar wrote:
> On 24 March 2014 14:30, Srikanth Thokala wrote:
>> Hi Jassi,
>>
>> Thanks for the Acked-by.
>>
>> On Mon, Mar 24, 2014 at 11:50 AM, Jassi Brar
>> wrote:
>>> On Tue, Mar 18
Hi Jassi,
Thanks for the Acked-by.
On Mon, Mar 24, 2014 at 11:50 AM, Jassi Brar wrote:
> On Tue, Mar 18, 2014 at 12:36 AM, Srikanth Thokala wrote:
>
>> +
>> +/**
>> + * xilinx_vdma_prep_slave_sg - prepare a descriptor for a DMA_SLAVE
>
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
nges in v3:
- Created a separate patch for the DT binding documentation as suggested by
Vinod, Thanks.
- Added support for interleaved frames with non-contiguous memory as suggested
by Lars, Thanks.
- Rebased on v3.14.0-rc2
Srikanth Thokala (2):
dma: Add Xilinx Video DMA DT Binding Documentation
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as
On Sat, Mar 15, 2014 at 12:11 AM, Andy Shevchenko
wrote:
> On Fri, 2014-03-14 at 23:20 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as suggested by Arnd
s with non-contiguous memory as suggested
by Lars, Thanks.
- Rebased on v3.14.0-rc2
Srikanth Thokala (2):
dma: Add Xilinx Video DMA DT Binding Documentation
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 75 ++
d
On Wed, Mar 12, 2014 at 12:02 AM, Srikanth Thokala wrote:
> On Tue, Mar 11, 2014 at 7:14 PM, Jassi Brar
> wrote:
>> On 11 March 2014 00:00, Srikanth Thokala wrote:
>>> On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar
>>> wrote:
>>>> On Thu, Mar 6, 2014
On Tue, Mar 11, 2014 at 7:14 PM, Jassi Brar wrote:
> On 11 March 2014 00:00, Srikanth Thokala wrote:
>> On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar wrote:
>>> On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
>>>
>>>>
On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar wrote:
> On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
>
>> +static struct dma_async_tx_descriptor *
>> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
>> +struct dma_
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as suggested by Arnd Bergmann
y' as
suggested by Jaswinder, Thanks.
Changes in v3:
- Created a separate patch for the DT binding documentation as suggested by
Vinod, Thanks.
- Added support for interleaved frames with non-contiguous memory as suggested
by Lars, Thanks.
- Rebased on v3.14.0-rc2
Srikanth Thokala (2):
dma:
On Mon, Mar 3, 2014 at 11:13 PM, Jason Gunthorpe
wrote:
> On Mon, Mar 03, 2014 at 07:10:36PM +0530, Srikanth Thokala wrote:
>
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representa
Please ignore the last message, accidentally it was sent. Apologies.
Srikanth
On Mon, Mar 3, 2014 at 11:43 PM, Srikanth Thokala wrote:
> On Mon, Mar 3, 2014 at 11:13 PM, Jason Gunthorpe
> wrote:
>> On Mon, Mar 03, 2014 at 07:10:36PM +0530, Srikanth Thokala wrote:
>>
>&g
On Mon, Mar 3, 2014 at 11:13 PM, Jason Gunthorpe
wrote:
> On Mon, Mar 03, 2014 at 07:10:36PM +0530, Srikanth Thokala wrote:
>
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representa
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
- Rebased on v3.14.0-rc5
- Removed IP specific DT properties like include-rc, axibar-num etc.,
as suggested by Jason and Bjorn, Thanks
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 23
On Wed, Feb 26, 2014 at 8:32 PM, Jassi Brar wrote:
> On 26 February 2014 23:21, Srikanth Thokala wrote:
>> On Mon, Feb 24, 2014 at 7:39 AM, Jassi Brar
>> wrote:
>>> On 21 February 2014 23:37, Srikanth Thokala wrote:
>>>> On Thu, Feb 20, 2014 at 3:23 PM,
On Mon, Feb 24, 2014 at 7:39 AM, Jassi Brar wrote:
> On 21 February 2014 23:37, Srikanth Thokala wrote:
>> On Thu, Feb 20, 2014 at 3:23 PM, Jassi Brar
>> wrote:
>>> On 20 February 2014 14:54, Srikanth Thokala wrote:
>>>> On Wed, Feb 19, 2014 at 12:33 AM,
Hi Jason,
On Fri, Feb 21, 2014 at 9:58 PM, Jason Gunthorpe
wrote:
> On Fri, Feb 21, 2014 at 08:18:00PM +0530, Srikanth Thokala wrote:
>
>> 00:00.0 Class 0604: Device 10ee:7081
>
> So this is great, a root port bridge is exactly correct - I would
> recommend using device 1
On Thu, Feb 20, 2014 at 11:15 PM, Jason Gunthorpe
wrote:
> On Thu, Feb 20, 2014 at 12:39:48PM +0530, Srikanth Thokala wrote:
>
>> > These should use the standard ranges mechanism for translations and
>> > apertures.
>>
>> This AXI PCIe bridge IP do have
On Wed, Feb 19, 2014 at 12:33 AM, Jassi Brar wrote:
> On 18 February 2014 23:16, Srikanth Thokala wrote:
>> On Tue, Feb 18, 2014 at 10:20 PM, Jassi Brar
>> wrote:
>>> On 18 February 2014 16:58, Srikanth Thokala wrote:
>>>> On Mon, Feb 17, 2014 at 3:27 PM,
On Wed, Feb 19, 2014 at 6:05 AM, Jason Gunthorpe
wrote:
> On Tue, Feb 18, 2014 at 02:32:58PM -0700, Bjorn Helgaas wrote:
>> [+cc Arnd]
>>
>> On Sun, Feb 16, 2014 at 8:33 AM, Srikanth Thokala wrote:
>> > This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
On Tue, Feb 18, 2014 at 10:20 PM, Jassi Brar wrote:
> On 18 February 2014 16:58, Srikanth Thokala wrote:
>> On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar
>> wrote:
>>> On 15 February 2014 17:30, Srikanth Thokala wrote:
>>>> The current implementation of
On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar wrote:
> On 15 February 2014 17:30, Srikanth Thokala wrote:
>> The current implementation of interleaved DMA API support multiple
>> frames only when the memory is contiguous by incrementing src_start/
>> dst_start members of
On Mon, Feb 17, 2014 at 3:14 PM, Lars-Peter Clausen wrote:
> On 02/17/2014 10:42 AM, Srikanth Thokala wrote:
>>
>> On Mon, Feb 17, 2014 at 3:05 PM, Lars-Peter Clausen
>> wrote:
>>>
>>> On 02/17/2014 10:29 AM, Srikanth Thokala wrote:
>>>>
&g
On Mon, Feb 17, 2014 at 3:05 PM, Lars-Peter Clausen wrote:
> On 02/17/2014 10:29 AM, Srikanth Thokala wrote:
>>
>> On Mon, Feb 17, 2014 at 2:13 PM, Vinod Koul wrote:
>>>
>>> On Sat, Feb 15, 2014 at 05:30:17PM +0530, Srikanth Thokala wrote:
>>>>
>&
On Mon, Feb 17, 2014 at 2:13 PM, Vinod Koul wrote:
> On Sat, Feb 15, 2014 at 05:30:17PM +0530, Srikanth Thokala wrote:
>> The current implementation of interleaved DMA API support multiple
>> frames only when the memory is contiguous by incrementing src_start/
>> dst_start m
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
- Rebased on v3.14.0-rc2
---
.../devicetree/bindings/pci/xilinx-pcie.txt| 43 +
drivers/pci/host/Kconfig |7 +
drivers/pci/host/Makefile
Lars, Thanks.
- Rebased on v3.14.0-rc2
Srikanth Thokala (3):
dma: Support multiple interleaved frames with non-contiguous memory
dma: Add Xilinx Video DMA DT Binding Documentation
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
.../devicetree/bindings/dma/xilinx
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as suggested by Arnd Bergmann
---
.../devicetree/bindings/dma
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
patch handles this
issue by allowing the slave device to send array of interleaved dma
templates each having a different memory location.
Signed-off-by: Srikanth Thokala
---
Documentation/dmaengine.txt |2 +-
drivers/dma/imx-dma.c|3 ++-
drivers/dma/sirf
On Thu, Feb 6, 2014 at 9:23 PM, Lars-Peter Clausen wrote:
> On 02/06/2014 02:34 PM, Srikanth Thokala wrote:
>>
>> On Wed, Feb 5, 2014 at 10:00 PM, Lars-Peter Clausen
>> wrote:
>>>
>>> On 02/05/2014 05:25 PM, Srikanth Thokala wrote:
>>>>
&
On Wed, Feb 5, 2014 at 10:00 PM, Lars-Peter Clausen wrote:
> On 02/05/2014 05:25 PM, Srikanth Thokala wrote:
>>
>> On Fri, Jan 31, 2014 at 12:21 PM, Srikanth Thokala
>> wrote:
>>>
>>> Hi Vinod,
>>>
>>> On Tue, Jan 28, 2014 at 8:43 AM, V
On Fri, Jan 31, 2014 at 12:21 PM, Srikanth Thokala wrote:
> Hi Vinod,
>
> On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul wrote:
>> On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
>>> Hi Lars/Vinod,
>>> >> The question here i think wou
On Tue, Feb 4, 2014 at 10:58 AM, Vinod Koul wrote:
> On Fri, Jan 31, 2014 at 12:22:52PM +0530, Srikanth Thokala wrote:
>> >>> >> [...]
>> >>> >>> +/**
>> >>> >>> + * xilinx_vdma_device_control - Configure DMA channel of t
Hi Vinod,
On Mon, Jan 27, 2014 at 4:36 PM, Srikanth Thokala wrote:
> Hi Vinod,
>
> On Sun, Jan 26, 2014 at 7:29 PM, Vinod Koul wrote:
>> On Fri, Jan 24, 2014 at 02:24:27PM +0100, Lars-Peter Clausen wrote:
>>> On 01/24/2014 12:16 PM, Srikanth Thokala wrote:
>>> &
Hi Vinod,
On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul wrote:
> On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
>> Hi Lars/Vinod,
>> >> The question here i think would be waht this device supports? Is the
>> >> hardware
>> >> capab
Hi Lars/Vinod,
On Sun, Jan 26, 2014 at 11:09 PM, Lars-Peter Clausen wrote:
> On 01/26/2014 02:59 PM, Vinod Koul wrote:
>> On Fri, Jan 24, 2014 at 02:24:27PM +0100, Lars-Peter Clausen wrote:
>>> On 01/24/2014 12:16 PM, Srikanth Thokala wrote:
>>>> Hi Lars,
>>
Hi Vinod,
On Sun, Jan 26, 2014 at 7:29 PM, Vinod Koul wrote:
> On Fri, Jan 24, 2014 at 02:24:27PM +0100, Lars-Peter Clausen wrote:
>> On 01/24/2014 12:16 PM, Srikanth Thokala wrote:
>> > Hi Lars,
>> >
>> > On Thu, Jan 23, 2014 at 4:55 PM, Lars-Peter Clausen
Hi Lars,
On Thu, Jan 23, 2014 at 4:55 PM, Lars-Peter Clausen wrote:
> On 01/22/2014 05:52 PM, Srikanth Thokala wrote:
> [...]
>> +/**
>> + * xilinx_vdma_device_control - Configure DMA channel of the device
>> + * @dchan: DMA Channel pointer
>> + * @cmd: DMA contro
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