Srinivas Kandagatla
Signed-off-by: Sricharan R
---
drivers/dma/qcom/bam_dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 4b43844..8e90a40 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -799,6
Hi Christian,
On 6/20/2019 9:02 PM, Christian Lamparter wrote:
> Hello Sricharan,
>
> On Wednesday, June 19, 2019 4:42:11 PM CEST Sricharan R wrote:
>> On 6/15/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R
Hi Srini,
On 6/18/2019 10:20 PM, Srinivas Kandagatla wrote:
>
>
> On 18/06/2019 17:27, Sricharan R wrote:
>> The Macro's expect that buffer size is power of 2. So we are infact
>> passing the actual correct
>> size ( MAX_DESCRIPTORS + 1 = 4096)
> This w
Hi Christian,
On 6/15/2019 2:11 AM, Christian Lamparter wrote:
> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
>>> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
&
On 6/18/2019 8:42 PM, Srinivas Kandagatla wrote:
>
>
> On 18/06/2019 15:56, Sricharan R wrote:
>> So MAX_DESCRIPTORS is used in driver for masking head/tail pointers.
>> That's why we have to pass MAX_DESCRIPTORS + 1 so that it works
>> when the Mac
Hi Srini,
On 6/18/2019 8:20 PM, Srinivas Kandagatla wrote:
> Hi Sricharan,
>
> On 18/06/2019 08:13, Sricharan R wrote:
>> Hi Srini,
>>
>> On 6/14/2019 7:50 PM, Srinivas Kandagatla wrote:
>>> For some reason arguments to most of the circular buffers
>>
Hi Srini,
On 6/14/2019 7:50 PM, Srinivas Kandagatla wrote:
> For some reason arguments to most of the circular buffers
> macros are used in reverse, tail is used for head and vice versa.
>
> This leads to bam thinking that there is an extra descriptor at the
> end and leading to retransmitting de
Hi Christian,
On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>>>
Hi Bjorn,
On 6/8/2019 9:18 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhi
Hi Bjorn,
On 6/8/2019 9:02 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> This patch adds support for the global clock controller found on
>> the ipq6018 based devices.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: anu
On 6/8/2019 8:57 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> Signed-off-by: Sricharan R
>> Signed-off-by: speriaka
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
>> 1 file changed, 2 insertions
Hi Bjorn,
On 6/8/2019 8:56 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> Add initial pinctrl driver to support pin configuration with
>> pinctrl framework for ipq6018.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by:
Hi Christian,
On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-
Hi Sudeep,
On 6/5/2019 11:04 PM, Sudeep Holla wrote:
> On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-b
Hi Marc,
On 6/5/2019 10:56 PM, Marc Zyngier wrote:
> On 05/06/2019 18:16, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
&g
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
Signed-off-by: Sricharan R
Signed-off-by: speriaka
---
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree/bindings/arm/qcom.yaml
index f6316ab..7b19028 100644
--- a
These configs are required for booting kernel in qcom
ipq6018 boards.
Signed-off-by: Sricharan R
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d58351..abf64ee 100644
--- a/arch/arm64
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.
Signed-off-by: Sricharan R
Signed-off-by: Rajkumar Ayyasamy
Signed-off-by: speriaka
---
.../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++
drivers/pinctrl/qcom/Kconfig
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018
Add the compatible strings and the include file for ipq6018
gcc clock controller.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq6018-cp01
board.
Sricharan R (6):
pinctrl: qcom: Add ipq6018 pinctrl driver
dt-bindings: qcom: Add ipq6018 bindings
clk: qcom: Add DT bindings for ipq6018 gcc
Sorry, Got sb...@codeaurora.org wrong. Will fix and repost
Regards,
Sricharan
On 6/5/2019 10:45 PM, Sricharan R wrote:
> The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
> Gateways and Access Points.
>
> This series adds minimal board boot support for ipq6018-cp01
> board.
&
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
These configs are required for booting kernel in qcom
ipq6018 boards.
Signed-off-by: Sricharan R
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d58351..abf64ee 100644
--- a/arch/arm64
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018
Add the compatible strings and the include file for ipq6018
gcc clock controller.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405
Signed-off-by: Sricharan R
Signed-off-by: speriaka
---
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree/bindings/arm/qcom.yaml
index f6316ab..7b19028 100644
--- a
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.
Signed-off-by: Sricharan R
Signed-off-by: Rajkumar Ayyasamy
Signed-off-by: speriaka
---
.../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++
drivers/pinctrl/qcom/Kconfig
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq6018-cp01
board.
Sricharan R (6):
pinctrl: qcom: Add ipq6018 pinctrl driver
dt-bindings: qcom: Add ipq6018 bindings
clk: qcom: Add DT bindings for ipq6018 gcc
Hi Niklas,
On 4/4/2019 10:39 AM, Niklas Cassel wrote:
> From: Sricharan R
>
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the re
Hi Niklas,
On 10/22/2018 9:00 PM, Niklas Cassel wrote:
> On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
>> Hi Stephen,
>>
>> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
>>> Quoting Stephen Boyd (2018-10-17 08:44:12)
>>>> Quoting Sricharan R
Hi Stephen,
On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> Quoting Stephen Boyd (2018-10-17 08:44:12)
>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>
>>>
>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>> Yup, this patch seems to have fixed the hi
>>
>>
>> On 7 September 2018 10:57:34 BST, Sricharan R
>> wrote:
>>> Hi Craig,
>>>
>>>
>>>>> [v12]
>>>>> * Added my signed-off that was missing in some patches.
>>>>> * Added Bjorn's acked
gt;>
>>
>> On 7 September 2018 10:57:34 BST, Sricharan R
>> wrote:
>>> Hi Craig,
>>>
>>>
>>>>> [v12]
>>>>> * Added my signed-off that was missing in some patches.
>>>>> * Added Bjorn's acked that i
n, QSB and the top PLL are always a fixed rate and thus
>> only support one frequency each. These sources provide the lowest
>> frequencies for the CPUs. The HFPLLs are where we can make the CPU go
>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>> fast
Hi Rob,
On 8/17/2018 8:39 PM, Rob Herring wrote:
> Hi, this email is from Rob's (experimental) review bot. I found a couple
> of common problems with your patch. Please see below.
>
> On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
>> The kryo cpufreq driver reads
Hi Craig,
On 8/14/2018 5:42 PM, Sricharan R wrote:
> [v12]
> * Added my signed-off that was missing in some patches.
> * Added Bjorn's acked that i missed earlier.
>
Can you give this a try on your 8974 device and check if the
pvs version reporting, scaling for highe
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b
clocks.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/arm/msm/qcom,kpss
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,krait-cc.txt
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60
he 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Acked-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
Signed-off-by: Sr
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc
: Sricharan R
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244
infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60 i
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
.../
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
based qcom socs
cpufreq: qcom: Add suppor
Hi Rob,
On 8/7/2018 2:05 AM, Rob Herring wrote:
> On Fri, Aug 3, 2018 at 8:10 AM Sricharan R wrote:
>>
>> Add a new board dts for ipq8064-ap161.
>>
>> Signed-off-by: Sricharan R
>> ---
>> Documentation/devicetree/bindings/arm/qcom.tx
Add a new board dts for ipq8064-ap161.
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++
3 files changed, 10 insertions(+)
create mode 100644
The nodes in ipq8064-ap148.dts currently are common with
boards that we will add next. So move the common data to
ipq8064-v.1.0.dtsi.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 83 ++--
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 65
Add the dt nodes for enabling the leds and gpio-buttons.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 +
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 60
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++
3 files changed
Adding pcie,sdcc nodes and a new board file ipq8064-ap161
Sricharan R (5):
arm: dts: qcom: Add pcie nodes for ipq8064
arm: dts: qcom: Add sdcc nodes for ipq8064
arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
arm: dts: qcom: Add ipq8064-ap161.dts
arm: dts: qcom: Add led and gpio
The relevant data for sdcc.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 76 +
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e02d588..e78618e 100644
Adding the pcie nodes and pins.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 182
1 file changed, 182 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac..e02d588 100644
dency here.
>
> Fixes: 3a3d4163e0bf ("remoteproc: qcom: Introduce Hexagon V5 based WCSS
> driver")
> Signed-off-by: Arnd Bergmann
Oops, missed it. Sorry.
Acked-by: Sricharan R
Regards,
Sricharan
> ---
> drivers/remoteproc/Kconfig | 1 +
> 1 file changed, 1 insertio
Hi Thierry,
On 6/27/2018 3:01 PM, Thierry Escande wrote:
> Hi Sricharan,
>
> On 19/06/2018 15:45, Sricharan R wrote:
>> Sricharan R (2):
>> clk: qcom: Add safe switch hook for krait mux clocks
>> dt-bindings: cpufreq: Document operating-points-v2-krait
Fix all nodes to use proper GIC_* macros for the interrupt type and the
interrupt trigger settings to avoid the boot warnings.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 41 ++---
1 file changed, 24 insertions(+), 17 deletions(-)
diff
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names property newly
.../devicetr
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
[Thierry Escande: upd
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] updated to include clocks and clock-names property newly
.../devicetree/bi
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names properties newly
.../devicetree/bindings/clock/qcom,hfp
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
m-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document ope
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
[v2] Fixed Kconfig to remove SMD dependency and addressed
Vinod's comments.
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +-
drivers/remot
Hi Vinod,
On 6/7/2018 2:13 PM, Vinod wrote:
> On 06-06-18, 21:24, Bjorn Andersson wrote:
>> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>>
>>> So, wouldn't Kconfig syntax something like where we say:
>>> M if RPMSG_QCOM_GLINK_SMEM=m
>>> bool if RPMSG_QCOM_GLINK_SMEM=y
>>>
>>
>> If w
Hi Bjorn,
On 6/7/2018 11:18 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 22:29 PDT 2018, Sricharan R wrote:
>
>> Hi Bjorn,
>>
>> On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
>>> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>>>
>>>> On 06-06-18, 0
Hi Bjorn,
On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>
>> On 06-06-18, 09:17, Bjorn Andersson wrote:
>>> On Tue 05 Jun 05:56 PDT 2018, Sricharan R wrote:
>>>
>>>> Hi Vinod,
>>>>
>>&g
Hi Vinod,
On 6/6/2018 12:19 PM, Vinod wrote:
> Hi Sricharan,
>
> On 06-06-18, 12:09, Sricharan R wrote:
>
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>&
Hi Vinod,
On 6/5/2018 10:10 PM, Vinod Koul wrote:
> On 05-06-18, 18:26, Sricharan R wrote:
>> Hi Vinod,
>>
>> On 6/5/2018 11:49 AM, Vinod wrote:
>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>
>>>> +config QCOM_Q6V5_WCSS
>>>> +
Hi Vinod,
On 6/5/2018 11:49 AM, Vinod wrote:
> On 05-06-18, 11:12, Sricharan R wrote:
>
>> +config QCOM_Q6V5_WCSS
>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>> +depends on OF && ARCH_QCOM
>> +depend
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