[PATCH V2 0/7] Add PCIe support for IPQ8074

clock patches as it has picked up by Stephen Sivaprakash Murugesan (7): dt-bindings: PCI: qcom: Add ipq8074 Gen3 PCIe compatible dt-bindings: phy: qcom,qmp: Add ipq8074 PCIe Gen3 phy phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init phy: qcom-qmp: Add compatible for ipq8074 PCIe Gen

[PATCH V2 1/7] dt-bindings: PCI: qcom: Add ipq8074 Gen3 PCIe compatible

ipq8074 has two PCIe ports while the support for Gen2 PCIe port is already available add the support for Gen3 binding. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan

[PATCH V2 6/7] PCI: qcom: Add ipq8074 PCIe controller support

Add support for PCIe Gen3 port found in ipq8074 devices. Signed-off-by: Sivaprakash Murugesan --- drivers/pci/controller/dwc/pcie-qcom.c | 177 - 1 file changed, 176 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci

[PATCH V2 7/7] arm64: dts: ipq8074: Fixup PCIe dts nodes

ipq8074 PCIe nodes missing required properties to make them work. Add these properties. Signed-off-by: Sivaprakash Murugesan --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 -- 2 files changed, 78 insertions

[PATCH V2 4/7] phy: qcom-qmp: Add compatible for ipq8074 PCIe Gen3 qmp phy

ipq8074 has two PCIe ports, One Gen2 and one Gen3 ports. Since support for Gen2 phy is already available, add support for PCIe Gen3 phy. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- [V2] * Addressed

[PATCH V2 2/7] dt-bindings: phy: qcom,qmp: Add ipq8074 PCIe Gen3 phy

Add PCIe phy compatible for Gen3 PCIe port found in ipq8074 devices. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1

[PATCH V2 3/7] phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init

iakaruppan Signed-off-by: Sivaprakash Murugesan --- [V2] * Fixed commit message as commented by Vinod drivers/phy/qualcomm/phy-qcom-qmp.c | 16 +--- drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qco

[PATCH V2 5/7] PCI: qcom: Do PHY power on before PCIe init

the system would hang. So move phy_power_on API before PCIe init. Fixes: commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe") Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers/pci

Re: [PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy

Hi Vinod, On 7/13/2020 11:34 AM, Vinod Koul wrote: On 05-07-20, 14:47, Sivaprakash Murugesan wrote: ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy support already available for gen2 pcie ports add support for pcie gen3 port phy. Co-developed-by: Selvam Sathappan

Re: [PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init

On 7/13/2020 11:25 AM, Vinod Koul wrote: On 05-07-20, 14:47, Sivaprakash Murugesan wrote: There were some problem in ipq8074 gen2 pcie phy init sequence, fix Can you please describe these problems, it would help review to understand the issues and also for future reference to you Hi Vinod

[PATCH V3] dt-bindings: pci: convert QCOM pci bindings to YAML

Convert QCOM pci bindings to YAML schema Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- [V3] * Rebased V2 including recent patches from Ansuel * Addressed Review comments from Rob * Apart from properties commented by Rob interrupt-map is also removed as it is documented

Re: [PATCH V2] dt-bindings: pci: convert QCOM pci bindings to YAML

Hi Rob, On 7/28/2020 9:24 PM, Rob Herring wrote: On Tue, Jul 28, 2020 at 9:27 AM Rob Herring wrote: On Sun, Jul 26, 2020 at 9:07 AM Sivaprakash Murugesan wrote: From: Sivaprakash Murugesan Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- [v2

Re: linux-next: manual merge of the devicetree tree with the pci tree

On 7/28/2020 11:19 AM, Stephen Rothwell wrote: Hi all, Today's linux-next merge of the devicetree tree got a conflict in: Documentation/devicetree/bindings/pci/qcom,pcie.txt between commits: 736ae5c91712 ("dt-bindings: PCI: qcom: Add missing clks") b11b8cc161de ("dt-bindings: PCI: qc

[PATCH V2] dt-bindings: pci: convert QCOM pci bindings to YAML

From: Sivaprakash Murugesan Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- [v2] - Referenced pci-bus.yaml - removed duplicate properties already referenced by pci-bus.yaml - Addressed comments from Rob .../devicetree/bindings/pci/qcom,pcie.txt

[PATCH] clk: qcom: ipq8074: Add correct index for PCIe clocks

The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by: kernel test robot Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 6

[PATCH 2/4] reset: qcom: ipq8074: Add ipq8074 gcc resets

Add gcc resets found in ipq8074 devices. These were previously added along with clock bindings. Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/reset/qcom,gcc-ipq8074.h | 141 +++ 1 file changed, 141 insertions(+) create mode 100644 include/dt-bindings

[PATCH 1/4] clk: qcom: ipq8074: remove gcc reset bindings

Remove ipq8074 gcc reset bindings from gcc clock bindings file, so that it can be added in reset bindings. This will avoid confusion while adding new clock and resets. Reported-by: kernel test robot Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 139

[PATCH 0/4] Split ipq8074 reset bindings from clock bindings

clock patches in https://lwn.net/Articles/825325/ are applied to clk-next it would be better if all the changes in this series to go through clk-next. Sivaprakash Murugesan (4): clk: qcom: ipq8074: remove gcc reset bindings reset: qcom: ipq8074: Add ipq8074 gcc resets arm64: dts: ipq8074

[PATCH 4/4] clk: qcom: ipq8074: include gcc reset bindings

Include gcc reset bindings in ipq8074 gcc clock controller Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 443e28cda8ed..dbc10b6ebac2 100644 --- a

[PATCH 3/4] arm64: dts: ipq8074: include reset bindings

Include gcc reset bindings in ipq8074 device tree Signed-off-by: Sivaprakash Murugesan --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5303821300b4..be2690c31433

[PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie

Add missing clock bindings for pcie port0 of ipq8074. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 4 1 file changed, 4 insertions(+) diff --git a

[PATCH 9/9] arm64: dts: ipq8074: Fixup pcie dts nodes

ipq8074 pcie nodes missing several properties which is needed to make them work add these properties. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8

[PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init

Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers/phy/qualcomm/phy-qcom-qmp.c | 16 +--- drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-q

[PATCH 7/9] pci: dwc: qcom: do phy power on before pcie init

the system would hang. So move phy_power_on API before pcie init API. Fixes: commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe") Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- driver

[PATCH 8/9] pci: qcom: Add support for ipq8074 pci controller

ipq8074 has one gen2 and one gen3 pcie port, with support for gen2 port is already available add support for pcie gen3 port. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers/pci/controller/dwc/pcie

[PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy

ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy support already available for gen2 pcie ports add support for pcie gen3 port phy. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers

[PATCH 2/9] dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy

ipq8074 has two different phy blocks for two pcie ports, with pcie gen2 compatible already available, specify the pcie phy compatible for gen3 pcie port. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan

[PATCH 4/9] clk: qcom: ipq8074: Add missing clocks for pcie

Add missing clocks and resets for pcie port0 of ipq8074 devices. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/gcc-ipq8074.c | 60 ++ 1 file

[PATCH 0/9] Add PCIe support for IPQ8074

/2020/6/24/162 Sivaprakash Murugesan (9): dt-bindings: pci: Add ipq8074 gen3 pci compatible dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy clk: qcom: ipq8074: Add missing bindings for pcie clk: qcom: ipq8074: Add missing clocks for pcie phy: qcom-qmp: use correct

[PATCH 1/9] dt-bindings: pci: Add ipq8074 gen3 pci compatible

ipq8074 has two PCIe ports while the support for gen2 pcie port is already available add the support for gen3 binding. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- .../devicetree/bindings/pci/qcom

[PATCH] dt-bindings: pci: convert QCOM pci bindings to YAML

Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- .../devicetree/bindings/pci/qcom,pcie.txt | 330 --- .../devicetree/bindings/pci/qcom,pcie.yaml | 470 + 2 files changed, 470 insertions(+), 330 deletions

[PATCH 2/3] crypto: qce: re-initialize context on import

sub squent hash request fails and qce hangs. To avoid this re-initialize request context on import. The qce import API alreasy takes care of taking the input vectors from passed io vec. Signed-off-by: Sivaprakash Murugesan --- drivers/crypto/qce/sha.c | 16 1 file changed, 12

[PATCH 3/3] crypto: qce: sha: Do not modify scatterlist passed along with request

s are higher. To avoid this, in qce do not mark the end of scatterlist in update API, the qce_ahash_async_req_handle API already takes care of this copying right amount of buffer from the request scatter list. Signed-off-by: Sivaprakash Murugesan --- drivers/crypto/qce/sha.c | 2 -- 1 file chang

[PATCH 1/3] crypto: qce: support zero length test vectors

crypto test module passes zero length vectors as test input to sha-1 and sha-256. To provide correct output for these vectors, hash zero support has been added as in other crypto drivers. Signed-off-by: Sivaprakash Murugesan --- drivers/crypto/Kconfig | 2 ++ drivers/crypto/qce/common.h

[PATCH 0/3] qce crypto fixes for tcrypto failures

while running tcrypto test cases on qce crypto engine few failures are noticed, this is mainly because of the updates on tcrypto driver and not testing qce reqgularly with mainline tcrypto driver. This series tries to address few of the errors while running tcrypto on qce. Sivaprakash Murugesan

[PATCH V8 2/4] clk: qcom: Add ipq apss pll driver

The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/Kconfig| 8 drivers/clk/qcom/Makefile | 1

[PATCH V8 3/4] clk: qcom: Add DT bindings for ipq6018 apss clock controller

Add dt-binding for ipq6018 apss clock controller Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- [V8] * took Ack from Rob include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h

[PATCH V8 0/4] Add APSS clock controller support for IPQ6018

ocumentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (4): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT

[PATCH V8 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible

cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- [V8] * converted compatible strings from const to enum to avoid dt binding error * retained Rob's review tag as the chan

[PATCH V8 4/4] clk: qcom: Add ipq6018 apss clock controller

The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by: Stephen Boyd Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom

Re: [PATCH V7 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible

On 6/20/2020 6:06 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-06-06 03:55:04) cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Signed-off-by: Sivaprakash Murugesan --- [V7] * Addressed minor review comment from Rob

Re: linux-next: Fixes tag needs some work in the pinctrl tree

Hi Linus, I just sent version2 of this patch with correct fixes tag. please pick it up. Thanks, Siva On 6/16/2020 4:42 PM, Stephen Rothwell wrote: Hi all, In commit 912f25eca000 ("pinctrl: qcom: ipq6018 Add missing pins in qpic pin group") Fixes tag Fixes: ef1ea54 (pinctrl: qcom:

[PATCH V2] pinctrl: qcom: ipq6018 Add missing pins in qpic pin group

The patch adds missing qpic data pins to qpic pingroup. These pins are necessary for the qpic nand to work. Fixes: ef1ea54eab0e ("pinctrl: qcom: Add ipq6018 pinctrl driver") Signed-off-by: Sivaprakash Murugesan --- [V2] * Corrected Fixes tag drivers/pinctrl/qcom/pinctrl-ipq6018.c

Re: [PATCH V3 0/5] Enable USB support in IPQ8074

Hi Vinod, Bjorn This series is completely reviewed and acked now, can you take this for merging? On 6/16/2020 3:57 PM, Sivaprakash Murugesan wrote: Ping! Hi Vinod, can you please review this patch series? On 6/8/2020 7:41 PM, Sivaprakash Murugesan wrote: IPQ8074 has two super speed USB

Re: [PATCH V7 0/4] Add APSS clock controller support for IPQ6018

Ping! Hi Stephen, Is it possible for you to review this series? We have regulators and few other patches depend on this patch, it would be great if you could provide your inputs on this. Thanks, Siva On 6/6/2020 4:25 PM, Sivaprakash Murugesan wrote: The CPU on Qualcomm's IP

Re: [PATCH V3 0/5] Enable USB support in IPQ8074

Ping! Hi Vinod, can you please review this patch series? On 6/8/2020 7:41 PM, Sivaprakash Murugesan wrote: IPQ8074 has two super speed USB ports, with QMP and QUSB2 PHYs. This patch set enables the USB PHYs and USB dwc3 in IPQ8074. [V3] * Rebased patch 3 on 5.7 and linux-next tag next

[PATCH V4 0/2] Fix issues related to register access in IPQ NAND

[V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove write to unavailable register mtd: rawnand: qcom: set BAM mode only if not set already drivers/mtd/nand/raw/qcom_nandc.c | 11

[PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register

NAND controller) Cc: sta...@vger.kernel.org Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index f1daf33..78b5f21 100644

[PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already

mode was already enabled by the bootloader, and enable BAM mode only if it is not enabled already. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd

[PATCH V3 0/2] Fix issues related to register access in IPQ NAND

Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V3] * Addressed review comments from Miquel [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash

[PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already

by bootloader, and set BAM mode only if it is not set already. Signed-off-by: Sivaprakash Murugesan --- [V3] * Changed commit message to give a small info about BAM drivers/mtd/nand/raw/qcom_nandc.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw

[PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register

IPQ4019 QPIC NANDcontroller) Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) Cc: sta...@vger.kernel.org Signed-off-by: Sivaprakash Murugesan --- [V3] * Addressed Miquel comments, added flag based on nand controller hw to avoid the register writes to specific ipq

Re: [PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register

Hi Miquel, On 6/9/2020 7:32 PM, Miquel Raynal wrote: Hi Sivaprakash, Sivaprakash Murugesan wrote on Tue, 9 Jun 2020 16:40:55 +0530: SFLASHC_BURST_CFG register is not available on all ipq nand platforms, it is available only on ipq8064 devices and the nand controller works without

Re: [PATCH V2 2/2] mtd: rawnand: qcom: set BAM mode only if not set already

Hi Miquel, Thanks for the review. On 6/9/2020 7:33 PM, Miquel Raynal wrote: Hi Sivaprakash, Sivaprakash Murugesan wrote on Tue, 9 Jun 2020 16:40:56 +0530: BAM mode is set by writing BAM_MODE_EN bit on NAND_CTRL register. NAND_CTRL is an operational register and in BAM mode operational

[PATCH] arm64: dts: ipq8074: enable sdhci node

Enable mmc device found on ipq8074 devices Signed-off-by: Sivaprakash Murugesan --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 22 ++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01

[PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register

SFLASHC_BURST_CFG register is not available on all ipq nand platforms, it is available only on ipq8064 devices and the nand controller works without configuring these registers in this platform, so register write to this can be removed. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand

[PATCH V2 0/2] Fix issues related to register access in IPQ NAND

Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove

[PATCH V2 2/2] mtd: rawnand: qcom: set BAM mode only if not set already

. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index e0afa2c..7740059 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c

[PATCH V3 1/5] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings

Add ipq8074 qmp phy device compatible for super speed usb support. Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp

[PATCH V3 2/5] dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible

Add ipq8074 compatible in QUSB2 PHY for high speed USB support. Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml

[PATCH V3 4/5] phy: qcom-qusb2: Add ipq8074 device compatible

Add ipq8074 qusb2 device compatible for high speed usb support. Signed-off-by: Sivaprakash Murugesan --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 393011a

[PATCH V3 5/5] arm64: dts: ipq8074: enable USB support

IPQ8074 has two super speed usb ports, add phy and dwc3 nodes to enable them. Signed-off-by: Sivaprakash Murugesan --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 167 ++ 2 files changed, 191 insertions(+) diff

[PATCH V3 3/5] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074

Add QMP USB PHY found in IPQ8074 Co-developed-by: Balaji Prakash J Signed-off-by: Balaji Prakash J Reviewed-by: Bjorn Andersson Signed-off-by: Sivaprakash Murugesan --- drivers/phy/qualcomm/phy-qcom-qmp.c | 102 1 file changed, 102 insertions(+) diff

[PATCH V3 0/5] Enable USB support in IPQ8074

ts on dts and binding Sivaprakash Murugesan (5): dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 phy: qcom-qusb2: Add ipq8074 device compatible arm64: dts: ipq8074: enabl

[PATCH] pinctrl: qcom: ipq6018 Add missing pins in qpic pin group

The patch adds missing qpic data pins to qpic pingroup. These pins are necessary for the qpic nand to work. Fixes: ef1ea54 (pinctrl: qcom: Add ipq6018 pinctrl driver) Signed-off-by: Sivaprakash Murugesan --- drivers/pinctrl/qcom/pinctrl-ipq6018.c | 3 ++- 1 file changed, 2 insertions(+), 1

[PATCH] mtd: raw: qcom_nand: Fix register write error

NAND_CTRL should be performed through BAM command descriptors. The NAND BAM mode will be enabled by bootloaders. Check if BAM mode is already enabled and enable it only if not enabled already. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 11 --- 1

Re: [PATCH V2 3/3] mailbox: qcom: Add ipq6018 apcs compatible

Hi Jassi, On 6/8/2020 2:15 AM, Jassi Brar wrote: On Sat, Jun 6, 2020 at 5:59 AM Sivaprakash Murugesan wrote: The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the apcs provides a clock controller functionality similar to msm8916 but the clock driver is different. Create

[PATCH V3 3/4] mailbox: qcom: Add clock driver name in apcs mailbox driver data

supporting the clock feature move the clock driver name inside the driver data. so that we can use a single API to get the register offset of mailbox driver and clock driver name together, and the clock driver will be added based on the driver data. Signed-off-by: Sivaprakash Murugesan --- drivers

[PATCH V3 0/4] Add ipq6018 apcs mailbox driver

from this series, will send it separately Sivaprakash Murugesan (3): dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block mailbox: qcom: Add ipq6018 apcs compatible .../bindings/mailbox/qcom,apcs-kpss-globa

[PATCH V3 4/4] mailbox: qcom: Add ipq6018 apcs compatible

The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the ipq6018 apcs provides a clock functionality similar to msm8916 but the clock driver is different. Create a child device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash

[PATCH V3 1/4] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block

Qualcomm APCS global block provides a bunch of generic properties which are required in a device tree. Add YAML schema for these properties. Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88

[PATCH V3 2/4] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block

Add dt-bindings for ipq6018 mailbox driver Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox

[PATCH V2 3/3] mailbox: qcom: Add ipq6018 apcs compatible

: Sivaprakash Murugesan --- [V2] * created a new structur for driver data. * re-arranged compatible strings in sorted order drivers/mailbox/qcom-apcs-ipc-mailbox.c | 61 +++-- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc

[PATCH V2 1/3] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block

Qualcomm APCS global block provides a bunch of generic properties which are required in a device tree. Add YAML schema for these properties. Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88

[PATCH V2 0/3] Add ipq6018 apcs mailbox driver

/27/637 [V2] * Addressed Bjorn's review comment, created a new structure for driver data. * Re-arranged compatible string based on sort order. * dropped dts patch from this series, will send it separately Sivaprakash Murugesan (3): dt-bindings: mailbox: Add YAML schemas for QCOM

[PATCH V2 2/3] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block

Add dt-bindings for ipq6018 mailbox driver Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox

[PATCH V7 2/4] clk: qcom: Add ipq apss pll driver

The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/Kconfig| 8 drivers/clk/qcom/Makefile | 1

[PATCH V7 4/4] clk: qcom: Add ipq6018 apss clock controller

The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by: Stephen Boyd Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom

[PATCH V7 0/4] Add APSS clock controller support for IPQ6018

the mux and enable belongs to the apcs block and PLL has a separate HW block. * Converted qcom mailbox and qcom a53 pll documentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch

[PATCH V7 3/4] clk: qcom: Add DT bindings for ipq6018 apss clock controller

Add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss

[PATCH V7 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible

cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Signed-off-by: Sivaprakash Murugesan --- [V7] * Addressed minor review comment from Rob .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++ 1 file changed, 18

Re: [PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller

On 6/2/2020 1:06 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-06-01 05:41:15) On 5/28/2020 7:29 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-05-27 05:24:51) diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c new file mode 100644

Re: [PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller

Hi Stepen, On 5/28/2020 7:29 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-05-27 05:24:51) diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c new file mode 100644 index 000..004f7e1 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -0,0 +1,106

[PATCH 2/4] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block

Add dt-bindings for ipq6018 mailbox driver Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox

[PATCH 4/4] arm64: dts: ipq6018: Add support for apcs clk

The ipq6018 devices has a clock functionality in apcs blcok. Add support for the clock found in ipq6018 apcs block. Signed-off-by: Sivaprakash Murugesan --- * This patch has compilation dependency with apss pll https://lkml.org/lkml/2020/5/27/642 arch/arm64/boot/dts/qcom/ipq6018.dtsi

[PATCH 1/4] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block

Qualcomm APCS global block provides a bunch of generic properties which are required in a device tree. Add YAML schema for these properties. Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88

[PATCH 3/4] mailbox: qcom: Add ipq6018 apcs compatible

: Sivaprakash Murugesan --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index eeebafd..db3f9518 100644 --- a/drivers/mailbox/qcom

[PATCH 0/4] Add ipq6018 apcs mailbox driver

/27/637 The patch 4 has dtb dependency with apss pll driver which can be found in https://lkml.org/lkml/2020/5/27/637 Sivaprakash Murugesan (4): dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block mailbox: qcom

[PATCH V6 1/5] dt-bindings: clock: add ipq6018 a53 pll compatible

cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Signed-off-by: Sivaprakash Murugesan --- * [V6] re-ordered compatible string, dropped Rob's review tag for this change. .../devicetree/bindings/clock/qcom,a53pll.yaml

[PATCH V6 2/5] clk: qcom: Add ipq apss pll driver

The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan --- [V6] * Addressed review comments from Stephen drivers/clk/qcom/Kconfig| 8

[PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller

The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by: Stephen Boyd Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom

[PATCH V6 5/5] arm64: dts: ipq6018: Add support for apss pll

Enable apss pll support. Signed-off-by: Sivaprakash Murugesan --- [V6] * split the mailbox driver from this patch arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi

[PATCH V6 3/5] clk: qcom: Add DT bindings for ipq6018 apss clock controller

Add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- [V6] * Addressed review comment from Stephen include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h

[PATCH V6 0/5] Add APSS clock controller support for IPQ6018

d Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (5): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: A

Re: [PATCH V5 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller

On 5/27/2020 8:00 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-05-24 03:04:42) add dt-binding for ipq6018 apss clock controller Capitalize 'add' because it starts the sentence. ok. Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-

[PATCH V5 3/8] clk: qcom: Add ipq apss pll driver

The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/Kconfig| 8 drivers/clk/qcom/Makefile | 1

[PATCH V5 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller

add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss

[PATCH V5 6/8] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block

Add dt-bindings for ipq6018 mailbox driver Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox

[PATCH V5 5/8] clk: qcom: Add ipq6018 apss clock controller

The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Signed-off-by: Sivaprakash Murugesan --- [V5] * Addressed Bjorn's review com

[PATCH V5 7/8] mailbox: qcom: Add ipq6018 apcs compatible

: Sivaprakash Murugesan --- [V5] * Addressed Bjorn's review comments drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index ee

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