for you to add them.
Please only Cc: this email address, I don't want multiple copies of
everything.
--
Simon Arlott
problem is before claiming that their
Linux support is better, especially if specific chipsets are known to
have issues...
--
Simon Arlott
x27;t find a branch with those in
locally.
Please remove my *email address* from the source code and MODULE_AUTHOR
text.
Historical signed-off-by lines can be updated to:
Signed-off-by: Simon Arlott
--
Simon Arlott
On 2020-07-15 14:18, Álvaro Fernández Rojas wrote:
Add BCM63xx USBH PHY driver for BMIPS.
Signed-off-by: Álvaro Fernández Rojas
---
...
+MODULE_DESCRIPTION("BCM63xx USBH PHY driver");
+MODULE_AUTHOR("Álvaro Fernández Rojas ");
+MODULE_AUTHOR("Simon Arlott ");
+MO
e.
Signed-off-by: Simon Arlott
Cc: Park Ju Hyung
Cc: sta...@vger.kernel.org
Fixes: ca6bfcb2f6d9 ("libata: Enable queued TRIM for Samsung SSD 860")
---
drivers/ata/libata-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.
-2350-3eefc8c17801@0882a8b5-c6c3-11e9-b005-00805fc181fe/
--
Simon Arlott
e for power off if the other reboot methods
fail.
It is necessary to re-order the processing of DMI checks because this quirk
must apply even if a reboot= command line parameter is used as that's the
only way to specify a PCI mode reboot.
Signed-off-by: Simon Arlott
---
Previous patches to ma
s behaviour if "c" was used.
Signed-off-by: Simon Arlott
---
Previous patches to make scsi/sd stop before a reboot:
https://lore.kernel.org/lkml/499138c8-b6d5-ef4a-2780-4f750ed337d3@0882a8b5-c6c3-11e9-b005-00805fc181fe/
https://lore.kernel.org/lkml/e726ffd8-8897-4a79-c3d6
(sdkp, 0);
+ if (sdkp->device->manage_start_stop) {
+ if (system_state != SYSTEM_RESTART || stop_before_reboot) {
+ sd_printk(KERN_NOTICE, sdkp, "Stopping disk\n");
+ sd_start_stop_device(sdkp, 0);
+ }
}
}
--
2.17.1
--
Simon Arlott
?
In my case none of the SSDs are recording unexpected power loss if they
are stopped before the reboot, but the reboot won't necessarily be
instantaneous after the last stop command returns.
--
Simon Arlott
On 19/06/2020 00:31, Damien Le Moal wrote:
> On 2020/06/18 21:26, Simon Arlott wrote:
>> I haven't verified it, but the BIOS leaves the power off for several
>> seconds which should be long enough for the HDDs to spin down.
>>
>> I'm less concerned about tho
ill change the patch so that it doesn't distinguish between types of
disks.
The default will have to be the existing behaviour (don't stop disks)
because most reboots shouldn't result in a loss of power.
--
Simon Arlott
On 18/06/2020 08:21, Christoph Hellwig wrote:
> On Wed, Jun 17, 2020 at 07:49:57PM +0100, Simon Arlott wrote:
>> Avoiding a stop of the disk on a reboot is appropriate for HDDs because
>> they're likely to continue to be powered (and should not be told to spin
>> down
On 18/06/2020 09:36, Damien Le Moal wrote:
> On 2020/06/18 3:50, Simon Arlott wrote:
>> I need to use "reboot=p" on my desktop because one of the PCIe devices
>> does not appear after a warm boot. This results in a very cold boot
>> because the BIOS turns the PSU
On 17/06/2020 20:19, Bart Van Assche wrote:
> On 2020-06-17 11:49, Simon Arlott wrote:
>> @@ -3576,9 +3582,19 @@ static void sd_shutdown(struct device *dev)
>> sd_sync_cache(sdkp, NULL);
>> }
>>
>> -if (system_state != SYSTEM_RESTART &
ower loss to corrupt data depending
on the SSD model/firmware.
Cc: sta...@vger.kernel.org
Signed-off-by: Simon Arlott
---
Documentation/scsi/scsi-parameters.rst | 7 +++
drivers/scsi/sd.c | 22 +++---
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git
If the cdrom fails to be registered then the device minor should be
deallocated.
Signed-off-by: Simon Arlott
Cc: sta...@vger.kernel.org
---
On 30/05/2020 17:24, Bart Van Assche wrote:
> On 2020-05-30 02:33, Simon Arlott wrote:
>> If the cdrom fails to be registered then the device min
If the device minor cannot be allocated or the cdrom fails to be
registered then the mutex should be destroyed.
Signed-off-by: Simon Arlott
Fixes: 51a858817dcd ("scsi: sr: get rid of sr global mutex")
Cc: sta...@vger.kernel.org
---
On 30/05/2020 17:41, James Bottomley wrote:
> On Sa
If the cdrom fails to be registered then the device minor should be
deallocated.
Signed-off-by: Simon Arlott
---
drivers/scsi/sr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
index 8d062d4f3ce0..1e13c6a0f0ca 100644
--- a/drivers
If the device minor cannot be allocated or the cdrom fails to be
registered then the mutex should be destroyed.
Signed-off-by: Simon Arlott
---
drivers/scsi/sr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
index d2fe3fa470f9..8d062d4f3ce0 100644
Add replacement email address for the one on my expired domain.
Signed-off-by: Simon Arlott
---
I'd prefer not to be in this "list of email addresses to spam" but it
appears to be the only way to stop people searching for other addresses
to misuse after I had to let my domain expi
Commit-ID: c7c42ec2baa1de7ab3965e4f1bf5073bee6065e4
Gitweb: http://git.kernel.org/tip/c7c42ec2baa1de7ab3965e4f1bf5073bee6065e4
Author: Simon Arlott
AuthorDate: Sun, 22 Nov 2015 14:30:14 +
Committer: Thomas Gleixner
CommitDate: Mon, 8 Feb 2016 15:03:42 +0100
irqchips/bmips: Add
Commit-ID: 64e1741f92191a9d8c3949eff48a4670b440c9f8
Gitweb: http://git.kernel.org/tip/64e1741f92191a9d8c3949eff48a4670b440c9f8
Author: Simon Arlott
AuthorDate: Sun, 22 Nov 2015 14:30:14 +
Committer: Thomas Gleixner
CommitDate: Mon, 8 Feb 2016 11:45:21 +0100
irqchips/bmips: Add
tfs that is used
to determine which rootfs is newer and what its real offset/size is.
The CFE bootline is used to select a rootfs.
Signed-off-by: Simon Arlott
---
v4: Reorganised functions based on earlier new patches in the series,
no real logic changes other than having to check for nvram-
Move the NOR flash layout to a separate function to allow the NAND flash
layout to be supported.
Signed-off-by: Simon Arlott
---
v4: New patch.
drivers/mtd/bcm63xxpart.c | 54 ---
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a
.
Signed-off-by: Simon Arlott
---
v4: New patch.
drivers/mtd/bcm63xxpart.c | 38 ++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/bcm63xxpart.c b/drivers/mtd/bcm63xxpart.c
index eafbf52..41aa202 100644
--- a/drivers/mtd/bcm63xxpart.c
Extract image tag reading and CRC check to a separate function.
Signed-off-by: Simon Arlott
---
v4: New patch.
drivers/mtd/bcm63xxpart.c | 62 ++-
1 file changed, 40 insertions(+), 22 deletions(-)
diff --git a/drivers/mtd/bcm63xxpart.c b/drivers/mtd
Remove bcm63xx_nvram_get_psi_size() as it now has no users.
Signed-off-by: Simon Arlott
---
v4: New patch.
arch/mips/bcm63xx/nvram.c | 11 ---
arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h | 2 --
2 files changed, 13 deletions(-)
diff --git a/arch/mips
.
BCM963XX_DEFAULT_PSI_SIZE changes from SZ_64K to 64 because it will be
multiplied by SZ_1K later on.
Signed-off-by: Simon Arlott
---
v4: New patch.
drivers/mtd/Kconfig | 2 +-
drivers/mtd/bcm63xxpart.c | 72 +--
2 files changed, 58 insertions(+), 16 deletions
The "dual_image" and "inactive_flag" fields should be merged into a single
"image_sequence" field.
Signed-off-by: Simon Arlott
---
v4: New patch.
include/linux/bcm963xx_tag.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/include/
used on a board without CFE
or any flash).
Signed-off-by: Simon Arlott
---
v4: New patch.
drivers/mtd/bcm63xxpart.c| 6 ++
include/linux/bcm963xx_tag.h | 5 +
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/bcm63xxpart.c b/drivers/mtd/bcm63xxpart.c
index
Move Broadcom BCM963xx image tag data structure to include/linux/
so that drivers outside of mach-bcm63xx can use it.
Signed-off-by: Simon Arlott
---
v4: New patch.
MAINTAINERS | 1 +
arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h | 96
Use the common definition of the nvram structure from the header file
include/linux/bcm963xx_nvram.h instead of maintaining a separate copy.
Read the version 5 size of nvram data from memory and then call the
new checksum verification function from the header file.
Signed-off-by: Simon Arlott
Broadcom BCM963xx boards have multiple nvram variants across different
SoCs with additional checksum fields added whenever the size of the
nvram was extended.
Add this structure as a header file so that multiple drivers can use it.
Signed-off-by: Simon Arlott
---
v4: Move out of uapi.
Add
On 13/12/15 22:42, Simon Arlott wrote:
> The BCM963xx NAND flash boards have a different handling of the
> partition layout from the NOR flash boards. For NAND there are offsets
> for the partitions in nvram. Both types of boards use the same CFE
> bootloader, nvram format and image
numbers to later on).
v2: Use external struct bcm963xx_nvram definition for bcm963268part.
Removed support for the nand partition number field, it's not a
standard Broadcom field (was added by MitraStar Technology Corp.).
--
Simon Arlott
--
To unsubscribe from this list: sen
On 11/12/15 23:12, Jonas Gorski wrote:
> On Fri, Dec 11, 2015 at 11:02 PM, Simon Arlott wrote:
>> +#define BCM63XX_CFE_MAGIC_OFFSET 0x4e0
>> +#define BCM963XX_CFE_VERSION_OFFSET0x570
>> +#define BCM963XX_NVRAM_OFFSET 0x580
>
> You should decide
On 11/12/15 23:29, Jonas Gorski wrote:
> On Fri, Dec 11, 2015 at 11:24 PM, Simon Arlott wrote:
>> On 11/12/15 22:02, Jonas Gorski wrote:
>>> On Fri, Dec 11, 2015 at 10:54 PM, Simon Arlott wrote:
>>>> Broadcom BCM963xx boards have multiple nvram variants across diffe
On 11/12/15 22:02, Jonas Gorski wrote:
> Hi,
>
> On Fri, Dec 11, 2015 at 10:54 PM, Simon Arlott wrote:
>> Broadcom BCM963xx boards have multiple nvram variants across different
>> SoCs with additional checksum fields added whenever the size of the
>> nvram was extende
tfs that is used
to determine which rootfs is newer and what its real offset/size is.
The CFE bootline is used to select a rootfs.
Signed-off-by: Simon Arlott
---
v3: Use COMPILE_TEST.
Ensure that strings read from flash are null terminated and validate
bcm_tag integer values (this also
ecksum_high;
- nvram.checksum_high = 0;
+ check_len = BCM963XX_NVRAM_V5_SIZE;
+ expected_crc = nvram.checksum_v5;
+ nvram.checksum_v5 = 0;
}
crc = crc32_le(~0, (u8 *)&nvram, check_len);
--
2.1.4
--
Simon Arlott
--
To unsubscribe
Broadcom BCM963xx boards have multiple nvram variants across different
SoCs with additional checksum fields added whenever the size of the
nvram was extended.
Add this structure as a header file so that multiple drivers and userspace
can use it.
Signed-off-by: Simon Arlott
---
v3: Fix includes
On 11/12/15 02:58, Rob Herring wrote:
> On Wed, Dec 09, 2015 at 10:29:35PM +0000, Simon Arlott wrote:
>> The BCM6358 contains power domains controlled with a register. Power
>> domains are indexed by bits in the register. Power domain bits can be
>> interleaved with other stat
ach rootfs that is used
to determine which rootfs is newer and what its real offset/size is.
The CFE bootline is used to select a rootfs.
Signed-off-by: Simon Arlott
---
v2: Use external struct bcm963xx_nvram definition for bcm963268part.
Removed support for the nand partition number field,
Use an external common definition of the nvram structure.
Signed-off-by: Simon Arlott
---
Compile tested only (there is no support for brcmnand on mach-bcm63xx).
v2: Use external struct bcm963xx_nvram definition for bcm963268part.
arch/mips/bcm63xx/nvram.c | 32
The BCM963xx has multiple nvram variants across different SoCs with
additional checksum fields added whenever the size of the nvram was
extended.
Signed-off-by: Simon Arlott
---
v2: Use external struct bcm963xx_nvram definition for bcm963268part.
MAINTAINERS | 1
.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott
---
v2: Resend, no changes.
v1: Renamed from BCM63xx to BCM6345.
MAINTAINERS | 1 +
drivers/clk/bcm/Kconfig | 9 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm6345.c | 191
tatus bits and configurable clocks in the same
register.
Signed-off-by: Simon Arlott
---
v2: Added clock-indices, clock-output-names (from clock-bindings.txt),
these are required properties.
v1: Renamed from BCM63xx to BCM6345.
.../bindings/clock/brcm,bcm6345-gate-clk.txt
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have been cleared).
Signed-off-by: Simon Arlott
---
v3: Resend based on linux-next, no changes.
v2: Renamed to bcm6345, removed "mask" property (and the regmap register
size is always ass
Add device tree binding for the BCM6345 soft reset controller.
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have been cleared).
Signed-off-by: Simon Arlott
---
v3: Resend. Example has changed because usbh now has two compatible
strings and
On 10/12/15 17:41, Florian Fainelli wrote:
> Le 09/12/2015 13:55, Simon Arlott a écrit :
>> drivers/mtd/Kconfig | 21 +++
>> drivers/mtd/Makefile| 1 +
>> drivers/mtd/bcm963268part.c | 373
>>
>>
le mode 100644
index 000..f4654d7
--- /dev/null
+++ b/drivers/power/bcm6358-power.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the
gmac";
+ active-low;
+};
+
+periph_iddq: power-controller {
+ compatible = "brcm,bcm6368-power-controller",
"brcm,bcm6358-power-controller";
+ regmap = <&periph_cntl>;
+ offset = <0x4>;
+
+ #power-domain-cells = <1>;
+ power-domain-indices = <19>;
+ power-domain-names = "usbh";
+};
--
2.1.4
--
Simon Arlott
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
each rootfs that is used
to determine which rootfs is newer and what its real offset/size is.
The CFE bootline or nvram partition number is used to select a rootfs.
Signed-off-by: Simon Arlott
---
I'm aware that this is not compatible with the mtd partition/device tree
reorganisation patches a
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott
---
Resend, no changes.
drivers/mtd/nand/brcmnand/brcmnand.c | 64
1 file changed, 50 insertions(+), 14
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott
---
Changed "nand-intr-base" reg name to "nand-int-base".
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 i
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott
---
Changed "nand-intr-base" reg name to
this driver.
Signed-off-by: Simon Arlott
---
Rebased against linux-next-20151209, no other changes.
MAINTAINERS | 1 +
arch/mips/Kconfig| 1 +
arch/mips/bmips/irq.c| 10 +-
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile
Add device tree binding for the BCM6345 interrupt controller.
This controller is similar to the SMP-capable BCM7038 and
the BCM3380 but with packed interrupt registers.
Signed-off-by: Simon Arlott
---
Corrected example device name to be "interrupt-controller".
.../interrupt-contr
On Fri, December 4, 2015 21:04, Simon Arlott wrote:
> On Fri, December 4, 2015 14:30, Rob Herring wrote:
>> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>>> +periph_clk: periph_clk {
>>> + compatible = "brcm,bcm63168-gate-clk", &q
On Fri, December 4, 2015 16:04, Jonas Gorski wrote:
> On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott wrote:
>> + * "brcm,nand-bcm6368"
>> + - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm6368"
>> + - reg: (required)
On Thu, December 3, 2015 08:39, Philipp Zabel wrote:
> Am Mittwoch, den 02.12.2015, 21:03 + schrieb Simon Arlott:
>> +periph_soft_rst: reset-controller {
>> +compatible = "brcm,bcm63168-reset", "brcm,bcm6345-reset";
>> +regmap
On Fri, December 4, 2015 14:30, Rob Herring wrote:
> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>> +periph_clk: periph_clk {
>> +compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
>> +regmap = <&periph_cntl>
On Fri, December 4, 2015 11:00, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:51:16PM +0000, Simon Arlott wrote:
>> On 03/12/15 23:45, Mark Brown wrote:
>
>> > Are you *sure* these are regulators and not power domains? These names
>> > look a lot like they could
On 03/12/15 23:45, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 11:38:28PM +0000, Simon Arlott wrote:
>
>> #define MISC_IDDQ_CTRL_GMAC (1<<18)
>> #define MISC_IDDQ_CTRL_WLAN_PADS(1<<13)
>> #define MISC_IDDQ_CTRL_PCIE (1<<12)
>
On 03/12/15 15:05, Mark Brown wrote:
> On Thu, Dec 03, 2015 at 08:14:33AM +0000, Simon Arlott wrote:
>> On 03/12/15 00:06, Mark Brown wrote:
>
>> > this it should know at least something about how to control the device
>> > from the compatible string. If you'r
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 insertions(+)
create mode 100644 drivers/mtd/nand/brcmnand/bcm6368_nand.c
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott
---
Removed ctrl->clk not NULL check.
drivers/mtd/nand/brcmnand/brcmnand.c | 64
1 file changed, 50 inse
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott
---
.../devicetree/bindings/mtd/brcm,brcmnand.txt
The BCM6345 contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott
---
Renamed
"phymips", "gmac", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk";
+ regmap = <&timer_cntl>;
+ offset = <0x4>
On 03/12/15 00:06, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 08:26:36PM +0000, Simon Arlott wrote:
>> On 02/12/15 12:53, Mark Brown wrote:
>
>> > This is the sort of thing you can pick up from the SoC compatible
>> > strings. As things stand there is ze
, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott
---
Renamed from BCM63268, moved clock to brcmnand.
drivers/mtd/nand/brcmnand/Makefile | 1 +
drivers/mtd/nand/brcmnand/bcm6368_nand.c | 145 +++
2 files changed, 146 insertions(+)
create mode
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott
---
drivers/mtd/nand/brcmnand/brcmnand.c | 69
1 file changed, 54 insertions(+), 15 deletions(-)
diff --git
Add device tree binding for NAND on the BCM6368.
The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.
Signed-off-by: Simon Arlott
---
Renamed from BCM63268, made clock a generic
pages at all. I don't know if
the controller will still return an uncorrectable error if the page is
erased but has 1 or more bit flips.
--
Simon Arlott
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile| 17 +++---
drivers/reset/bcm
Add device tree binding for the BCM6345 soft reset controller.
The BCM6345 contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
Renamed to bcm6345, removed "mask" property.
.../bindings/reset/brcm,bcm6345
On 02/12/15 18:03, Florian Fainelli wrote:
> 2015-11-30 12:58 GMT-08:00 Simon Arlott :
>> The BCM63xx contains a soft-reset controller activated by setting
>> a bit (that must previously have cleared).
>>
>> Signed-off-by: Simon Arlott
>> ---
>> MAINTAINER
On 02/12/15 20:21, Brian Norris wrote:
> Hi Simon,
>
> On Wed, Dec 02, 2015 at 08:12:32PM +0000, Simon Arlott wrote:
>> On 02/12/15 20:00, Brian Norris wrote:
>> > On Wed, Dec 02, 2015 at 07:41:07PM +, Simon Arlott wrote:
>> >> I've created a bcm963268
On 02/12/15 12:53, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 12:45:50PM -0000, Simon Arlott wrote:
>> On Tue, December 1, 2015 22:16, Mark Brown wrote:
>
>> > Why are these in the DT, I would expect that if this is a driver for a
>> > specific SoC all these propert
On 01/12/15 10:41, Jonas Gorski wrote:
> On Sat, Nov 28, 2015 at 8:23 PM, Simon Arlott wrote:
>> +
>> + /* Go to start of buffer */
>> + buf -= FC_WORDS;
>> +
>> + /* Erased if all data bytes are 0xFF */
>> + buf_erased =
On 02/12/15 20:00, Brian Norris wrote:
> Hi,
>
> On Wed, Dec 02, 2015 at 07:41:07PM +0000, Simon Arlott wrote:
>> >> + nand0: nandcs@0 {
>> >> + compatible = "brcm,nandcs";
>> >> +
>> >> + #address-cells = <0>
On 02/12/15 19:38, Florian Fainelli wrote:
> 2015-12-02 11:05 GMT-08:00 Brian Norris :
>> + Broadcom list + Kamal
>>
>> On Tue, Nov 24, 2015 at 08:19:37PM -, Simon Arlott wrote:
>>> Add device tree binding for NAND on the BCM63268.
>>>
>>>
On 02/12/15 19:18, Brian Norris wrote:
> + Broadcom list + Kamal
>
> Hi Simon,
>
> On Wed, Nov 25, 2015 at 07:49:13PM +0000, Simon Arlott wrote:
>> The BCM63268 has a NAND interrupt register with combined status and enable
>> registers. It also has a clock for the NA
On 02/12/15 19:05, Brian Norris wrote:
> + Broadcom list + Kamal
>
> On Tue, Nov 24, 2015 at 08:19:37PM -0000, Simon Arlott wrote:
>> Add device tree binding for NAND on the BCM63268.
>>
>> The BCM63268 has a NAND interrupt register with combined status and enable
>
On Tue, December 1, 2015 22:16, Mark Brown wrote:
> On Mon, Nov 30, 2015 at 08:30:07PM +0000, Simon Arlott wrote:
>
>> +- offset: register offset
>> +- mask: register enable mask
>> +- startup-delay-us: startup time in microseconds
>
> Why are these in the DT, I
Add of_match_table for "brcm,bcm6345-wdt".
Use a NULL clock name when not on mach-bcm63xx so that the device tree
clock name does not have to be "periph".
Allow the watchdog to be selected on BMIPS_GENERIC and select the BCM6345
timer interrupt handler.
Signed-off-by: Simon
rfere with the watchdog if an interrupt occurs) and remove its
exported functions.
Use the timer interrupt directly in bcm63xx_wdt.
Signed-off-by: Simon Arlott
---
arch/mips/bcm63xx/dev-wdt.c| 7 +
arch/mips/bcm63xx/timer.c
machine types.
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
arch/mips/bcm63xx/prom.c | 1 +
arch/mips/bcm63xx/setup.c | 1 +
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 22
Warn when the device is registered if the hardware watchdog is currently
running and report the remaining time left.
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog
Return the remaining time from the hardware control register.
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 0a19731..ab4a794 100644
--- a
Instead of using a fixed clock HZ in the driver, obtain it from the
"periph" clk that the watchdog timer uses.
Signed-off-by: Simon Arlott
Reviewed-by: Florian Fainelli
---
drivers/watchdog/bcm63xx_wdt.c | 36 +++-
1 file changed, 31 insertions(+), 5
Convert bcm63xx_wdt to use WATCHDOG_CORE.
The default and maximum time constants that are only used once have been
moved to the initialisation of the struct watchdog_device.
Signed-off-by: Simon Arlott
---
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/bcm63xx_wdt.c | 259
,
reducing the maximum timeout from 256 seconds to 85 seconds
(2^32 / WDT_HZ).
Signed-off-by: Simon Arlott
---
drivers/watchdog/bcm63xx_wdt.c | 125 -
1 file changed, 73 insertions(+), 52 deletions(-)
diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog
Add device tree binding for the BCM6345 watchdog.
This uses the BCM6345 timer for its warning interrupt.
Signed-off-by: Simon Arlott
Acked-by: Rob Herring
---
.../bindings/watchdog/brcm,bcm6345-wdt.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
added later if required without changing the device
tree binding.
Signed-off-by: Simon Arlott
---
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-bcm6345-l2-timer.c | 386 +
3 files changed, 392
Add device tree bindings for the BCM6345/BCM6318 timers. This is required
for the BCM6345 watchdog which needs to respond to one of the timer
interrupts.
Signed-off-by: Simon Arlott
Acked-by: Rob Herring
---
.../bindings/timer/brcm,bcm6318-timer.txt | 44
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile| 1 +
drivers/reset/reset-bcm63xx.c | 134
Add device tree binding for the BCM63xx soft reset controller.
The BCM63xx contains a soft-reset controller activated by setting
a bit (that must previously have cleared).
Signed-off-by: Simon Arlott
---
.../bindings/reset/brcm,bcm63xx-reset.txt | 37 ++
1 file
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