On 4/8/2021 1:01 PM, Ruiqi Gong wrote:
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Reported-by: Hulk Robot
Signed-off-by: Ruiqi Gong
---
drivers/thermal/thermal_mmio.c | 5 +
1 file changed, 1 insertion(+
On 8/16/2020 2:22 PM, Borislav Petkov wrote:
CAUTION: This email originated from outside of the organization. Do not click
links or open attachments unless you can confirm the sender and know the
content is safe.
On Sun, Aug 16, 2020 at 12:17:31PM +0300, Shenhar, Talel wrote:
Let me know
On 8/15/2020 9:33 PM, Borislav Petkov wrote:
On Tue, Jul 28, 2020 at 12:51:55PM +0300, Talel Shenhar wrote:
+static void al_mc_edac_check(struct mem_ctl_info *mci)
+{
+ struct al_mc_edac *al_mc = mci->pvt_info;
+
+ if (al_mc->irq_ue <= 0)
+ handle_ue(mci);
+
+ if (al_mc
On 7/27/2020 9:14 PM, Rob Herring wrote:
On Sun, 26 Jul 2020 22:15:54 +0300, Talel Shenhar wrote:
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding.
Signed-off-by: Talel Shenhar
Reviewed-by: Rob Herring
---
.../bindings/edac/amazon,al-mc-edac.yaml | 52 +
On 5/5/2020 1:44 PM, Shenhar, Talel wrote:
On 4/28/2020 2:06 PM, Borislav Petkov wrote:
On Mon, Feb 24, 2020 at 03:41:31PM +0200, Talel Shenhar wrote:
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding.
Signed-off-by: Talel Shenhar
Reviewed-by: Rob He
On 5/4/2020 9:37 PM, Borislav Petkov wrote:
On Mon, May 04, 2020 at 01:16:10PM +0300, Shenhar, Talel wrote:
+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
+ sizeof(struct al_mc_edac));
You can let that line stick out.
I rather avoid having this as a
Rob and other DT folks,
Can you please help with below query?
On 4/28/2020 2:06 PM, Borislav Petkov wrote:
On Mon, Feb 24, 2020 at 03:41:31PM +0200, Talel Shenhar wrote:
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding.
Signed-off-by: Talel Shenhar
Reviewed-by: Rob Herrin
On 4/28/2020 2:06 PM, Borislav Petkov wrote:
On Mon, Feb 24, 2020 at 03:41:31PM +0200, Talel Shenhar wrote:
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding.
Signed-off-by: Talel Shenhar
Reviewed-by: Rob Herring
---
.../bindings/edac/amazon,al-mc-edac.yaml | 52 +++
On 10/21/2019 7:42 PM, James Morse wrote:
Hi Talel,
On 10/10/2019 12:41, Talel Shenhar wrote:
The Amazon's Annapurna Labs SoCs includes Point Of Serialization error
logging unit that reports an error in case write error (e.g . Attempt to
(This is tricky to parse. "error in case write error"
Thanks Rob,
On 10/11/2019 4:29 PM, Rob Herring wrote:
On Thu, Oct 10, 2019 at 02:54:13PM +0300, Talel Shenhar wrote:
Document Amazon's Annapurna Labs Memory Controller EDAC SoC binding.
Signed-off-by: Talel Shenhar
---
.../bindings/edac/amazon,al-mc-edac.yaml | 50
Thanks for the review
On 10/10/2019 2:29 AM, Rob Herring wrote:
On Mon, Oct 07, 2019 at 03:47:14PM +0300, Talel Shenhar wrote:
Document Amazon's Annapurna Labs POS SoC binding.
Signed-off-by: Talel Shenhar
---
.../bindings/edac/amazon,al-pos-edac.yaml | 40 ++
zon's Annapurna Labs Memory Controller EDAC
+
+maintainers:
+ - Talel Shenhar
+ - Talel Shenhar
+
+description: |
+ EDAC node is defined to describe on-chip error detection and correction for
+ Amazon's Annapurna Labs Memory Controller.
+
+properties:
+
+ compatible:
+- const: &qu
thanks for the review
On 10/7/2019 2:26 PM, Marc Zyngier wrote:
On Thu, 03 Oct 2019 12:32:41 +0100,
Talel Shenhar wrote:
+ log1 = readl(al_pos->mmio_base + AL_POS_ERROR_LOG_1);
I already commented on the misuse of strict accesses. Unless you can
explain and document *why* you need the e
thanks for the review.
On 10/4/2019 6:05 PM, Rob Herring wrote:
On Thu, Oct 3, 2019 at 6:33 AM Talel Shenhar wrote:
Fails 'make dt_binding_check' (drop the '-'):
ack, shall be part of v5
+
+examples:
+ - |
+al_pos_edac@f0070084 {
edac@...
ack, shall be part of v5
+ compatibl
On 9/19/2019 5:42 PM, James Morse wrote:
Hi guys,
On 12/09/2019 10:19, Shenhar, Talel wrote:
On 9/12/2019 11:50 AM, Marc Zyngier wrote:
On Thu, 12 Sep 2019 07:50:03 +0100,
"Shenhar, Talel" wrote:
On 9/11/2019 5:15 PM, Marc Zyngier wrote:
On Tue, 10 Sep 2019 20:05:09 +0100,
Tal
Thanks for the review.
On 9/18/2019 8:47 PM, James Morse wrote:
Hi Talel,
On 15/09/2019 07:43, Talel Shenhar wrote:
The Amazon's Annapurna Labs Memory Controller EDAC supports ECC capability
for error detection and correction (Single bit error correction, Double
detection). This driver introd
Tnx Rob for the review.
Shall be part of v3.
Waiting for responses from Arnd and James and will publish v3.
On 9/18/2019 4:35 PM, Rob Herring wrote:
On Tue, Sep 10, 2019 at 10:05:08PM +0300, Talel Shenhar wrote:
Document Amazon's Annapurna Labs POS SoC binding.
Signed-off-by: Talel Shenhar
On 9/12/2019 11:50 AM, Marc Zyngier wrote:
On Thu, 12 Sep 2019 07:50:03 +0100,
"Shenhar, Talel" wrote:
Hi Marc,
On 9/11/2019 5:15 PM, Marc Zyngier wrote:
[+James]
Hi Talel,
On Tue, 10 Sep 2019 20:05:09 +0100,
Talel Shenhar wrote:
+ log1 = readl(pos-
On 9/11/2019 5:18 PM, Marc Zyngier wrote:
On Tue, 10 Sep 2019 20:05:10 +0100,
Talel Shenhar wrote:
Fix wrap around for pos errors on addresses above 32 bit.
Reported-by: kbuild test robot
Signed-off-by: Talel Shenhar
---
drivers/soc/amazon/al_pos.c | 2 +-
1 file changed, 1 insertion(+)
Hi Marc,
On 9/11/2019 5:15 PM, Marc Zyngier wrote:
[+James]
Hi Talel,
On Tue, 10 Sep 2019 20:05:09 +0100,
Talel Shenhar wrote:
+ log1 = readl(pos->mmio_base + AL_POS_ERROR_LOG_1);
Do you actually need the implied barriers? I'd expect that relaxed
accesses should be enough.
You are
On 9/9/2019 6:16 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 4:11 PM Shenhar, Talel wrote:
On 9/9/2019 4:41 PM, Arnd Bergmann wrote:
In current implementation of v1, I am not doing any read barrier, Hence,
using the non-relaxed will add unneeded memory barrier.
I have no strong
On 9/9/2019 6:08 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 3:59 PM Shenhar, Talel wrote:
On 9/9/2019 4:45 PM, Arnd Bergmann wrote:
Its not that something will get broken. its error event detector for POS
events which allows seeing bad accesses to registers.
What is the general rule
On 9/9/2019 4:41 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 1:13 PM Shenhar, Talel wrote:
On 9/9/2019 12:44 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 11:14 AM Talel Shenhar wrote:
+ writel_relaxed(0, pos->mmio_base + AL_POS_ERROR_LOG_1);
Why do you require _rela
On 9/9/2019 4:45 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 12:17 PM Shenhar, Talel wrote:
On 9/9/2019 12:40 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 11:14 AM Talel Shenhar wrote:
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4778c77..bd86b15
On 9/9/2019 12:44 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 11:14 AM Talel Shenhar wrote:
The Amazon's Annapurna Labs SoCs includes Point Of Serialization error
logging unit that reports an error in case write error (e.g. attempt to
write to a read only register).
This patch introduces
On 9/9/2019 12:40 PM, Marc Zyngier wrote:
On Mon, 09 Sep 2019 09:39:18 +0100,
Talel Shenhar wrote:
Hi Talel,
Introduce interrupts retrigger support for Amazon's Annapurna Labs Fabric
Interrupt Controller.
Signed-off-by: Talel Shenhar
---
drivers/irqchip/irq-al-fic.c | 12
On 9/9/2019 12:40 PM, Arnd Bergmann wrote:
On Mon, Sep 9, 2019 at 11:14 AM Talel Shenhar wrote:
Amazon's Annapurna Labs SoCs uses al-pos driver, enable it.
Signed-off-by: Talel Shenhar
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig
On 7/10/2019 7:45 PM, Jonathan Chocron wrote:
Document Amazon's Annapurna Labs PCIe host bridge.
That is the way! (best to keep same wordings (Amazon's)
Signed-off-by: Jonathan Chocron
---
.../devicetree/bindings/pci/pcie-al.txt | 45 +++
MAINTAINERS
Thanks, will do.
On 7/9/2019 11:15 AM, Marc Zyngier wrote:
On 09/07/2019 06:59, Shenhar, Talel wrote:
Marc, should I publish those fixes as new patch that updates the
dt-bindings or new patchset to this list?
If you are going to update the binding, please submit a patch on top of
mainline
Marc, should I publish those fixes as new patch that updates the
dt-bindings or new patchset to this list?
On 7/9/2019 5:23 AM, Rob Herring wrote:
On Mon, Jun 10, 2019 at 11:34:42AM +0300, Talel Shenhar wrote:
+- #interrupt-cells: must be 2.
+ First cell defines the index of the interrupt wit
Disagree. The various drivers don't depend on each other.
I think we should keep the drivers separated as they are distinct and
independent IP blocks.
But they don't exist in isolation, they both depend on the
integration-choices/firmware
that makes up your platform.
Other platforms may hav
On 6/5/2019 6:12 PM, Marc Zyngier wrote:
On 05/06/2019 15:38, Shenhar, Talel wrote:
FIC only support two sensing modes, rising-edge and level.
Yes, I can tell. Yet, this code will let EDGE_BOTH pass through, even if
it cannot handle it.
Will handle on v4
Indeed we use interrupt specifier
On 6/5/2019 6:49 PM, Eduardo Valentin wrote:
On Wed, Jun 05, 2019 at 01:52:00PM +0300, Talel Shenhar wrote:
+- compatible: should be "amazon,al-fic"
+- reg: physical base address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cel
On 6/5/2019 3:50 PM, Greg KH wrote:
On Wed, Jun 05, 2019 at 01:52:01PM +0300, Talel Shenhar wrote:
--- /dev/null
+++ b/drivers/irqchip/irq-al-fic.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
No need for kernel-doc format style here.
done
+ * Copyright 2019 Amazon.com, Inc
Thanks, will publish the fixes on v3.
On 6/5/2019 3:22 PM, Marc Zyngier wrote:
Talel,
On 05/06/2019 11:52, Talel Shenhar wrote:
The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs
lines. A FIC (Fabric Interrupt Controller) may be cascaded into another FIC
Really? :-(
Casca
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