Hi Will,
On 03/27/2018 12:36 PM, Will Deacon wrote:
> Hi Shanker,
>
> On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
>> On 03/27/2018 06:34 AM, Robin Murphy wrote:
>>> On 27/03/18 04:21, Philip Elcan wrote:
>>>> Several of the bits of th
tic inline function rather than a macro,
> since it doesn't need to do any wacky type-dodging, but either way the
> overall change now looks appropriate;
>
> Acked-by: Robin Murphy
>
Tested-by: Shanker Donthineni
> Thanks,
> Robin.
>
>> +
>> /*
>>
Hi Marc,
On 03/22/2018 10:51 AM, Marc Zyngier wrote:
> On 22/03/18 01:58, Shanker Donthineni wrote:
>> The definition of the GICR_CTLR.RWP control bit was expanded to indicate
>> status of changing GICR_CTLR.EnableLPI from 1 to 0 is being in progress
>> or completed.
GICR_PROPBASER, otherwise behavior is UNPREDICTABLE.
Signed-off-by: Shanker Donthineni
---
Changes since v2:
-Revert readl_relaxed_poll() usage since it's not usable in GICv3 probe().
-Changes to pr_xxx messages.
Changes since v1:
-Moved LPI disable code to a seperate function as Marc sugg
Hi Marc,
On 03/17/2018 12:13 PM, Marc Zyngier wrote:
> On Sat, 17 Mar 2018 16:11:06 +,
> Shanker Donthineni wrote:
>>
>> Hi Marc,
>>
>> On 03/17/2018 08:34 AM, Marc Zyngier wrote:
>>> On Thu, 15 Mar 2018 09:31:27 -0500
>>> Shanker D
Hi Marc,
On 03/17/2018 08:34 AM, Marc Zyngier wrote:
> On Thu, 15 Mar 2018 09:31:27 -0500
> Shanker Donthineni wrote:
>
>> The definition of the GICR_CTLR.RWP control bit was expanded to indicate
>> status of changing GICR_CTLR.EnableLPI from 1 to 0 is being in pro
D_TYPER) &
> GICD_TYPER_LPIS);
> + return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) &
> GICD_TYPER_LPIS) && !gicv3_nolpi;
Thanks for this patch series especially for KDUMP case. It would be nice if we
disable GIC-ITS and
GICR-LPI functionality completely to avoid in
GICR_PROPBASER, otherwise behavior is UNPREDICTABLE.
Signed-off-by: Shanker Donthineni
---
Changes since v1:
-Moved LPI disable code to a seperate function as Marc suggested.
-Mark's suggestion to use readl_relaxed_poll_timeout() helper functions.
drivers/irqchip/irq-gic-v3-its.c
~(pageblock_nr_pages-1)) - 1;
>> +pfn = memblock_next_valid_pfn(pfn, end_pfn) - 1;
>> #endif
>> continue;
>> }
>> --
>> 2.15.1
>>
>>
>> __
Hi Marc,
On 03/14/2018 02:41 AM, Marc Zyngier wrote:
> Hi Shanker,
>
> On Wed, 14 Mar 2018 00:50:01 +,
> Shanker Donthineni wrote:
>>
>> The definition of the GICR_CTLR.RWP control bit was expanded to indicate
>> status of changing GICR_CTLR.EnableLPI from 1 t
GICR_PROPBASER, otherwise behavior is UNPREDICTABLE.
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v3-its.c | 30 +++---
include/linux/irqchip/arm-gic-v3.h | 1 +
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b
Hi Will,
On 03/09/2018 07:48 AM, Will Deacon wrote:
> Hi SHanker,
>
> On Mon, Mar 05, 2018 at 11:06:43AM -0600, Shanker Donthineni wrote:
>> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
>> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch
Hi Will,
On 03/06/2018 09:25 AM, Will Deacon wrote:
> On Mon, Mar 05, 2018 at 12:03:33PM -0600, Shanker Donthineni wrote:
>> On 03/05/2018 11:15 AM, Will Deacon wrote:
>>> On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
>>>> On 03/05/2018 09:56 A
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Co-authored-by: Philip Elcan
S
Hi Will,
On 03/06/2018 12:48 PM, Shanker Donthineni wrote:
> Hi Will,
>
> On 03/06/2018 09:23 AM, Will Deacon wrote:
>> Hi Shanker,
>>
>> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote:
>>> On 03/06/2018 07:44 AM, Will Deacon wrote:
>
Hi Will,
On 03/06/2018 09:23 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote:
>> On 03/06/2018 07:44 AM, Will Deacon wrote:
>>> I think this is a slight asymmetry with the code for the I-side. On the
&
Hi Will
On 03/06/2018 07:44 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable through new
Hi Will,
On 03/05/2018 11:15 AM, Will Deacon wrote:
> On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
>> Hi Will,
>>
>> On 03/05/2018 09:56 AM, Will Deacon wrote:
>>> Hi Shanker,
>>>
>>> On Fri, Mar 02, 2018 at 03:50:18PM -0
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
of Silicon provider service ID 0xC2001700.
Signed-off-by: Shanker Donthineni
---
Chnages since
Hi Will,
On 03/05/2018 09:56 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote:
>> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
>> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
of Silicon provider service ID 0xC2001700.
Signed-off-by: Shanker Donthineni
---
arch/arm64
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Co-authored-by: Philip Elcan
S
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan
S
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan
S
Hi Mark,
On 02/21/2018 09:09 AM, Mark Rutland wrote:
> On Wed, Feb 21, 2018 at 07:49:06AM -0600, Shanker Donthineni wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable through new fields in CTR_EL0.
>>
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan
S
Hi Catalin,
On 02/21/2018 05:12 AM, Catalin Marinas wrote:
> On Mon, Feb 19, 2018 at 08:59:06PM -0600, Shanker Donthineni wrote:
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index f55fe5b..4061210 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kco
fication is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan
S
Thanks Catalin for your comments.
On 02/19/2018 11:18 AM, Catalin Marinas wrote:
> On Mon, Feb 19, 2018 at 10:35:30AM -0600, Shanker Donthineni wrote:
>> On 02/19/2018 08:38 AM, Catalin Marinas wrote:
>>> On the patch, I'd rather have an alternative framework entry for
Hi Will,
On 02/19/2018 08:43 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote:
>> Two point of unification cache maintenance operations 'DC CVAU' and
>> 'IC IVAU' are optional for implementors
Hi Catalin,
On 02/19/2018 08:38 AM, Catalin Marinas wrote:
> On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote:
>> Two point of unification cache maintenance operations 'DC CVAU' and
>> 'IC IVAU' are optional for implementors as per ARMv8 spec
.
— CNTVCT is read from Non-secure EL0.
So, no need to zero CNTVOFF_EL2/CNTVOFF for VHE case.
Signed-off-by: Shanker Donthineni
---
virt/kvm/arm/arch_timer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 70268c0
unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan
Signed-off-by: Shanker Donthineni
---
arch/arm64/
References to CPU part number MIDR_QCOM_FALKOR were dropped from the
mailing list patch due to mainline/arm64 branch dependency. So this
patch adds the missing part number.
Fixes: ec82b567a74f ("arm64: Implement branch predictor hardening for Falkor")
Signed-off-by: Shanker Donthineni
Hi Will, Thanks for your quick reply.
On 02/01/2018 04:33 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Jan 31, 2018 at 06:03:42PM -0600, Shanker Donthineni wrote:
>> A DMB instruction can be used to ensure the relative order of only
>> memory accesses before and aft
ensures that no instructions that appear in program
order after the DSB instruction, can execute until the DSB instruction
has completed.
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic
/git/next/linux-next.git/commit/arch/arm64?h=next-20180112&id=ec82b567a74fbdffdf418d4bb381d55f6a9096af
[v2] https://www.spinics.net/lists/arm-kernel/msg627364.html
Thanks,
Shanker
On 01/08/2018 11:32 AM, Will Deacon wrote:
> From: Shanker Donthineni
>
> Falkor is susceptible to bra
eady
available in upstream v4.15-rc7
branch. Please merge v2 patch.
On 01/08/2018 01:10 PM, Shanker Donthineni wrote:
> Hi Will,
>
> On 01/08/2018 12:44 PM, Will Deacon wrote:
>> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
>>> On Fri, Jan 05, 2018 at
Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.
Signed-off-by: Shanker Donthineni
---
Changes since v1:
Corrected
d-off-by: Shanker Donthineni
Signed-off-by: Will Deacon
---
This patch is availble at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64?h=v4.15-rc7&id=c622cc013cece073722592cff1ac6643a33b1622
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 i
Hi Will,
On 01/08/2018 12:44 PM, Will Deacon wrote:
> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
>> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
>>> Falkor is susceptible to branch predictor aliasing and can
>>> theoretically be
Hi Andrew,
On 01/08/2018 03:28 AM, Andrew Jones wrote:
> Hi Shanker,
>
> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
> ...
>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index cb0fb37..daf53a5 100644
&g
Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.
Signed-off-by: Shanker Donthineni
---
This patch has been verified
d-off-by: Shanker Donthineni
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@
0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Changes since v3:
Rebased to kernel v4.15-rc3 and removed the alternatives
Thanks Mark, I'll post v5 patch without alternatives.
On 12/11/2017 04:45 AM, Mark Rutland wrote:
> Hi,
>
> On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
>> +/**
>> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
&
Hi Will,
I tested v2 patch series on Centriq2400 server platform successfully, no
regression so far. And also
we applied internal patches on top of the branch "kpti" and verified kaiser
feature.
Tested-by: Shanker Donthineni
--
Shanker Donthineni
Qualcomm Datacenter Technologie
0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Changes since v3:
Rebased to kernel v4.15-rc1.
Changes since v2:
Repost the
d-off-by: Shanker Donthineni
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@
Hi Marc,
I messed-up patch contents please disregard this one and review v4 patch.
[v4] irqchip/gic-v3: Fix the driver probe() fail due to disabled GICC entry
https://patchwork.kernel.org/patch/10093653/
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Hi Marc,
I messed-up patch contents please disregard this one and review v4 patch.
[v4] irqchip/gic-v3: Fix the driver probe() fail due to disabled GICC entry
https://patchwork.kernel.org/patch/10093653/
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
000
Signed-off-by: Shanker Donthineni
---
changes since v3:
Fix typo.
changes since v2:
Edited commit text.
changes since v1:
Added a new "if condition" to skip disabled GICC entry and edited commit.
drivers/irqchip/irq-gic-v3.c | 11 +++
1 file changed, 11 inserti
d : 00
Signed-off-by: Shanker Donthineni
---
changes since v1:
Edited commit text.
changes since v1:
Added a new "if condition" to skip disabled GICC entry and edited commit.
drivers/irqchip/irq-gic-v3.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/ir
4.13.5 #26
[] dump_backtrace+0x0/0x218
[] show_stack+0x14/0x20
[] dump_stack+0x98/0xb8
[] panic+0x118/0x26c
[] init_IRQ+0x24/0x2c
[] start_kernel+0x230/0x394
[] __primary_switched+0x64/0x6c
---[ end Kernel panic - not syncing: No interrupt controller found.
Signed-off-by: Shanker Donthineni
-
Hi Marc,
On 12/05/2017 02:59 AM, Marc Zyngier wrote:
> On 04/12/17 14:04, Shanker Donthineni wrote:
>> Hi Thanks,
>>
>> On 12/04/2017 04:28 AM, Marc Zyngier wrote:
>>> On 03/12/17 23:21, Shanker Donthineni wrote:
>>>> As per MADT specification, it
Hi Will,
On 12/03/2017 07:35 AM, Shanker Donthineni wrote:
> Hi Will, thanks for your review comments.
>
> On 12/01/2017 05:24 AM, Will Deacon wrote:
>> On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote:
>>> The ARM architecture defines the memory loca
Hi Thanks,
On 12/04/2017 04:28 AM, Marc Zyngier wrote:
> On 03/12/17 23:21, Shanker Donthineni wrote:
>> As per MADT specification, it's perfectly valid firmware can pass
>> MADT table to OS with disabled GICC entries. ARM64-SMP code skips
>> those cpu cores to bring o
Class : 00
Reserved : 00
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v3.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index b56c3e2..a30fbac 100644
---
Hi Will, thanks for your review comments.
On 12/01/2017 05:24 AM, Will Deacon wrote:
> On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote:
>> The ARM architecture defines the memory locations that are permitted
>> to be accessed as the result of a speculative in
series got dropped to accommodate review comments. Apply
the workaround where it's required.
Posted wrong the patches in v2.
Shanker Donthineni (2):
arm64: Define cputype macros for Falkor CPU
arm64: Add software workaround for Falkor erratum 1041
Documentation/arm64/silicon-errata.txt
d-off-by: Shanker Donthineni
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@
0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Changes since v3:
Rebased to kernel v4.15-rc1.
Changes since v2:
Repost the
Hi,
Sorry, I've posted a wrong patch which causes the compilation errors.
Please disregard this patch, I posted v3 patch to fix the build
issue.
https://patchwork.kernel.org/patch/10055077/
On 11/12/2017 07:16 PM, Shanker Donthineni wrote:
> The ARM architecture defines the memory l
d-off-by: Shanker Donthineni
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@
ratum E1041.
Shanker Donthineni (2):
arm64: Define cputype macros for Falkor CPU
arm64: Add software workaround for Falkor erratum 1041
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch/arm64/include/asm/assembler.h
0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Changes since v1:
Apply the workaround where it's required.
Changes sin
SCTLR_ELn[M] is changed to 0 to fix the
Falkor erratum 1041.
Patch2 from V1 series got dropped to accommodate review comments. Apply
the workaround where it's required.
Patch1:
- CPUTYPE definitions for Falkor CPU.
Patch2:
- Actual workaround changes for erratum E1041.
Shanker Donthine
d-off-by: Shanker Donthineni
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@
0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig
Hi James,
On 11/10/2017 04:24 AM, James Morse wrote:
> Hi Shanker,
>
> On 09/11/17 15:22, Shanker Donthineni wrote:
>> On 11/09/2017 05:08 AM, James Morse wrote:
>>> On 04/11/17 21:43, Shanker Donthineni wrote:
>>>> On 11/03/2017 10:11 AM, Robin Murphy wro
Hi James,
On 11/09/2017 05:08 AM, James Morse wrote:
> Hi Shanker, Robin,
>
> On 04/11/17 21:43, Shanker Donthineni wrote:
>> On 11/03/2017 10:11 AM, Robin Murphy wrote:
>>> On 03/11/17 03:27, Shanker Donthineni wrote:
>>>> The ARM architecture defines the
Hi Robin, Thanks for your review comments.
On 11/03/2017 10:11 AM, Robin Murphy wrote:
> On 03/11/17 03:27, Shanker Donthineni wrote:
>> The ARM architecture defines the memory locations that are permitted
>> to be accessed as the result of a speculative instruction fetch from
d-off-by: Shanker Donthineni
Signed-off-by: Neil Leeder
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/
This patch introduces two helper macros read_sctlr and write_sctlr
to access system register SCTLR_ELn. Replace all MSR/MRS references
to sctlr_el1{el2} with macros.
This should cause no behavioral change.
Signed-off-by: Shanker Donthineni
---
arch/arm64/include/asm/assembler.h | 18
executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch/arm64/include/asm/assembler.h | 17 +
arch/arm64/include/asm/cpucaps.h
SCTLR_ELn[M] is changed to 0 to fix the
Falkor erratum 1041.
Patch1:
- CPUTYPE definitions for Falkor CPU.
Patch2:
- Define two ASM helper macros to read/write SCTLR_ELn register.
Patch3:
- Actual workaround changes for erratum E1041.
Shanker Donthineni (3):
arm64: Define cputype macros for
b9407802 6b15005f 5440 (d421)
---[ end trace 4defdcd9ed65d530 ]---
Signed-off-by: Shanker Donthineni
---
Changes since v1:
-Added crash log messages to commit text.
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/
ister when ITS PageSize is 64KB:
-Bits[47:16] of the register provide bits[47:16] of the table PA.
-Bits[15:12] of the register provide bits[51:48] of the table PA.
-Bits[15:00] of the base physical address are 0.
Signed-off-by: Shanker Donthineni
---
Changes since v2:
-Few more changes from Marc
cated 65536 Virtual CPUs (flat, esz 8, psz 64K, shr 1)
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v3-its.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index cc7c8f6..7b98313 1
Hi Marc,
On 10/07/2017 07:59 AM, Shanker Donthineni wrote:
> Hi Marc,
>
> Thanks for your quick review comments.
>
> On 10/07/2017 04:58 AM, Marc Zyngier wrote:
>> On Sat, Oct 07 2017 at 12:13:24 am BST, Shanker Donthineni
>> wrote:
>>> The current ITS
ister when ITS PageSize is 64KB:
-Bits[47:16] of the register provide bits[47:16] of the table PA.
-Bits[15:12] of the register provide bits[51:48] of the table PA.
-Bits[15:00] of the base physical address are 0.
Signed-off-by: Shanker Donthineni
---
Changes since v1:
-Included Marc's sug
Hi Marc,
Thanks for your quick review comments.
On 10/07/2017 04:58 AM, Marc Zyngier wrote:
> On Sat, Oct 07 2017 at 12:13:24 am BST, Shanker Donthineni
> wrote:
>> The current ITS driver works fine as long as normal memory and GICR
>> regions are located within the lower 4
ister when ITS PageSize is 64KB:
-Bits[47:16] of the register provide bits[47:16] of the table PA.
-Bits[15:12] of the register provide bits[51:48] of the table PA.
-Bits[15:00] of the base physical address are 0.
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v
I posted v4 patch https://patchwork.kernel.org/patch/9989667/ with parentheses
around a macro parameter.
-Original Message-
From: Timur Tabi [mailto:ti...@codeaurora.org]
Sent: Friday, October 6, 2017 9:26 AM
To: Shanker Donthineni
Cc: Marc Zyngier ; linux-kernel
; linux-arm-kernel
with affinity level 0 values of 0-15 are supported.
0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
Signed-off-by: Shanker Donthineni
---
Changes since v3:
- Keep parentheses around a macro parameter.
Changes since v2:
- Changed from pr_crit() to pr_crit_once
with affinity level 0 values of 0-15 are supported.
0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
Signed-off-by: Shanker Donthineni
---
Changes since v2:
- Changed from pr_crit() to pr_crit_once().
- Incorporated Marc's simplified RSS validation check.
Ch
Hi Marc,
On 10/05/2017 05:43 AM, Marc Zyngier wrote:
> On 20/09/17 04:21, Shanker Donthineni wrote:
>> A new feature Range Selector (RS) has been added to GIC specification
>> in order to support more than 16 CPUs at affinity level 0. New fields
>> are introduced in
The driver probe path hits 'BUG_ON(entries != vpe_proxy.dev->nr_ites)'
on systems where it has VLPI capability, doesn't support direct LPI
feature and boot with a single CPU.
Relax the BUG_ON() condition to fix the issue.
Signed-off-by: Shanker Donthineni
---
drivers/irqchi
with affinity level 0 values of 0-15 are supported.
0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
Signed-off-by: Shanker Donthineni
---
Changes since v1:
- Addrssed Marc's review comments on RSS validation checks.
- Apply code changes to gic_compute_target
Hi Marc,
On 09/16/2017 01:14 PM, Marc Zyngier wrote:
> On Fri, Sep 15 2017 at 10:08:56 am BST, Shanker Donthineni
> wrote:
>
> Hi Shanker,
>
>> A new feature Range Selector (RS) has been added to GIC specification
>> in order to support more than 16 CPUs at affinity
with affinity level 0 values of 0-15 are supported.
0b1 = Targeted SGIs with affinity level 0 values of 0-255 are supported.
Signed-off-by: Shanker Donthineni
---
drivers/irqchip/irq-gic-v3.c | 79 --
include/linux/irqchip/arm-gic-v3.h | 4 ++
2 files
er.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Signed-off-by: Shanker Donthineni
---
arch/arm64/include/asm/esr.h | 4
arch/arm64/kvm/handle_exit.c | 12 +++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/es
On 07/10/2017 10:53 AM, Shanker Donthineni wrote:
> The NUMA node information is visible to ITS driver but not being used
> other than handling hardware errata. ITS/GICR hardware accesses to the
> local NUMA node is usually quicker than the remote NUMA node. How slow
> the remote N
-off-by: Shanker Donthineni
Tested-by: Ganapatrao Kulkarni
---
drivers/irqchip/irq-gic-v3-its.c | 36
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 45ea1933..40442fb
36 PM, Marc Zyngier wrote:
>>>>> On 10/07/17 09:48, Ganapatrao Kulkarni wrote:
>>>>>> Hi Marc,
>>>>>>
>>>>>> On Mon, Jul 3, 2017 at 8:23 PM, Marc Zyngier
>>>>>> wrote:
>>>>>>> H
ngier wrote:
>>>> On 10/07/17 09:48, Ganapatrao Kulkarni wrote:
>>>>> Hi Marc,
>>>>>
>>>>> On Mon, Jul 3, 2017 at 8:23 PM, Marc Zyngier wrote:
>>>>>> Hi Shanker,
>>>>>>
>>>>>> On 03/07/1
then we don't advertise KVM_CAP_MSI_DEVID capability.
Update the field msis_require_devid to true inside vgic_its_create()
to fix the issue.
Fixes: 0e4e82f154e3 ("vgic-its: Enable ITS emulation as a virtual MSI
controller")
Signed-off-by: Shanker Donthineni
---
virt/kvm/arm/vgic/v
kvm_for_each_vcpu(i, vcpu, kvm)
> kvm_vgic_vcpu_enable(vcpu);
> @@ -323,6 +329,9 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm)
>
> kfree(dist->spis);
> dist->nr_spis = 0;
> +
> + if (kvm_vgic_global_state.has_gicv4 &&
Hi Marc,
On 07/03/2017 09:53 AM, Marc Zyngier wrote:
> Hi Shanker,
>
> On 03/07/17 15:24, Shanker Donthineni wrote:
>> Hi Marc,
>>
>> On 06/30/2017 03:51 AM, Marc Zyngier wrote:
>>> On 30/06/17 04:01, Ganapatrao Kulkarni wrote:
>>>> On F
Hi Marc,
On 06/30/2017 03:51 AM, Marc Zyngier wrote:
> On 30/06/17 04:01, Ganapatrao Kulkarni wrote:
>> On Fri, Jun 30, 2017 at 8:04 AM, Ganapatrao Kulkarni
>> wrote:
>>> Hi Shanker,
>>>
>>> On Sun, Jun 25, 2017 at 9:16 PM, Shanker Donthineni
>>>
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