On Mon, Mar 29, 2021 at 6:27 AM Xin Ji wrote:
>
> On Thu, Mar 25, 2021 at 02:19:23PM -0400, Sean Paul wrote:
> > On Fri, Mar 19, 2021 at 2:35 AM Xin Ji wrote:
> > >
> > > Add HDCP feature, enable HDCP function through chip internal key
> > > and downstream&
On Fri, Mar 19, 2021 at 2:35 AM Xin Ji wrote:
>
> Add HDCP feature, enable HDCP function through chip internal key
> and downstream's capability.
>
> Signed-off-by: Xin Ji
> ---
> drivers/gpu/drm/bridge/analogix/anx7625.c | 147 ++
> drivers/gpu/drm/bridge/analogix/anx7625.h
On Mon, Feb 22, 2021 at 11:31 AM wrote:
>
> On 2021-02-19 14:46, Stephen Boyd wrote:
> > Quoting khs...@codeaurora.org (2021-02-19 08:39:38)
> >> On 2021-02-18 15:02, Stephen Boyd wrote:
> >> > Quoting Kuogee Hsieh (2021-02-18 12:55:04)
> >> >> Allow supported link rate to be limited to the value
account for
> the fact that downstream port caps can be either 1 byte or 4 bytes
> long. We can actually skip fixing the max_clock/max_bpc helpers here
> since they all check for DP_DETAILED_CAP_INFO_AVAILABLE anyway.
> * Fix ret code check for drm_dp_dpcd_read
>
Thanks for sortin
+{
> + int ret;
> +
> + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
> + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
> + return -EIO;
> +
> + ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
> +
if (ret < 0)
> return false;
>
> - /*
> - * Sink count can change between short pulse hpd hence
> - * a member variable in intel_dp will track any changes
> - * between s
vers can use them as well.
>
> Note that this also starts using intel_dp_has_sink_count() in
> intel_dp_detect_dpcd(), which is a functional change.
>
Reviewed-by: Sean Paul
> Signed-off-by: Lyude Paul
> ---
> drivers/gpu/drm/drm_dp_helper.c | 22
u8 real_edid_checksum);
>
> +int drm_dp_downstream_read_info(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
> int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> const u8 port_cap[4]);
> int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> --
> 2.26.2
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
On Tue, Aug 11, 2020 at 04:04:46PM -0400, Lyude Paul wrote:
> Just a tiny drive-by cleanup, we can consolidate i915's code for
> checking for MST support into a helper to be shared across drivers.
>
Reviewed-by: Sean Paul
> Signed-off-by: Lyude Paul
> ---
> drive
From: Sean Paul
These functions are all the same for dp and dp_mst, so move them into a
dedicated file for both sst and mst to use.
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-11-s...@poorly.run
#v1
Link:
https
On Tue, Aug 11, 2020 at 5:08 PM Rob Clark wrote:
>
> From: Rob Clark
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:817 dpu_crtc_enable() error:
> uninitialized symbol 'request_bandwidth'.
>
> Reported-by: kernel test robot
Reviewed-by: Sean Paul
> Signed-o
ubsystem to create their own tracing instance, and the
> trace_array_printk() only writes into those instances.
>
> Add trace_array_init_printk() to initialize the trace_printk() buffers
> without printing out the WARNING message.
>
> Reported-by: Sean Paul
> Signed-off-by:
he subsystem to create their own tracing instance, and the
> trace_array_printk() only writes into those instances.
>
> Add trace_array_init_printk() to initialize the trace_printk() buffers
> without printing out the WARNING message.
>
> Reported-by: Sean Paul
With the addition of
ere.
> >>>
> >>>>
> >>>> [1] drm_client_modeset_commit_atomic()
> >>>>
> >>>> Please also note that in a case of the scan-out rotation, plane's
> >>>> coordinates need to be changed in accordance to the
On Wed, Apr 29, 2020 at 4:57 AM Jani Nikula wrote:
>
> On Tue, 28 Apr 2020, Michal Orzel wrote:
> > As suggested by the TODO list for the kernel DRM subsystem, replace
> > the deprecated functions that take/drop modeset locks with new helpers.
> >
> > Signed-off-by: Michal Orzel
> > ---
> > dri
On Mon, Oct 21, 2019 at 03:01:56PM +, Mihail Atanassov wrote:
> I'll be the main point of contact.
>
> Cc: James Qian Wang (Arm Technology China)
> Cc: Liviu Dudau
> Signed-off-by: Mihail Atanassov
Acked-by: Sean Paul
> ---
> MAINTAINERS | 1 +
>
(struct msm_dsi_host
> *msm_host)
>
> /* dsi controller can only be reset while clocks are running */
> dsi_write(msm_host, REG_DSI_RESET, 1);
> - wmb(); /* make sure reset happen */
> + msleep(20); /* make sure reset happen */
> dsi_write(msm
allation orientation of the panel with respect to the
> > > > > chassis.
> > > > > + */
> > > > > + int orientation;
> > > > > +
> > > > > + /**
> > > > > + * @bus_formats
> > > > > + *
> > > > > + * Pixel data format on the wire.
> > > > > + */
> > > > > + const u32 *bus_formats;
> > > > > +
> > > > > + /**
> > > > > + * @num_bus_formats:
> > > > > + *
> > > > > + * Number of elements pointed to by @bus_formats
> > > > > + */
> > > > > + unsigned int num_bus_formats;
> > > > > +
> > > > > + /**
> > > > > + * @bus_flags:
> > > > > + *
> > > > > + * Additional information (like pixel signal polarity) for the
> > > > > pixel
> > > > > + * data on the bus.
> > > > > + */
> > > > > + u32 bus_flags;
> > > > > +
> > > > > /**
> > > > >* @list:
> > > > >*
> > >
> > > Thanks for the review
> >
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
--
Sean Paul, Software Engineer, Google / Chromium OS
On Mon, Oct 07, 2019 at 03:12:00PM -0700, dbasehore . wrote:
> On Mon, Oct 7, 2019 at 9:38 AM Sean Paul wrote:
> >
> > On Wed, Sep 25, 2019 at 03:58:30PM -0700, Derek Basehore wrote:
> > > This adds a helper function for reading the rotation (panel
> > >
atforms that need quirks.
>
> Signed-off-by: Derek Basehore
> Acked-by: Sam Ravnborg
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/drm_connector.c | 45 ++---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel
ton Li
> Cc: Imre Deak
> Cc: Ville Syrjälä
> Cc: Harry Wentland
> Cc: Daniel Vetter
> Signed-off-by: Lyude Paul
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 17 ++---
> 1 file changed, 10 insertions(+), 7 deletions(-)
&g
and
> Reviewed-by: Daniel Vetter
> Signed-off-by: Lyude Paul
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
On Thu, Aug 29, 2019 at 09:45:17AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> In addition, moving to kms->flush_commit() lets us drop the only user
> of kms->commit().
>
> Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/ms
se will no longer be
> a good place to enable/disable clocks needed for hw access.
>
> Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 17 ++---
> drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 19 ++
b Clark
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 41 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 3 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 +++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_enco
me
(ie: DRM_DISPLAY_MODE_LEN)? This still seems unsafe.
Sean
> } else {
> ret = drm_mode_parse_cmdline_res_mode(name, mode_end,
> parse_extras,
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
On Thu, May 16, 2019 at 03:00:01PM +0300, Laurent Pinchart wrote:
> Hi Sean,
>
> On Mon, May 13, 2019 at 10:38:58AM -0400, Sean Paul wrote:
> > On Sat, May 11, 2019 at 3:12 PM Laurent Pinchart wrote:
> > > On Thu, May 02, 2019 at 03:49:46PM -0400, Sean Paul wrote
On Thu, May 02, 2019 at 03:53:36PM -0700, Douglas Anderson wrote:
> Veyron uses the builtin i2c controller that's part of dw-hdmi. Hook
> up the unwedging feature.
>
> Signed-off-by: Douglas Anderson
Reviewed-by: Sean Paul
> ---
>
> arch/arm/boot/dts/rk3288-vey
rl-names = "default", "unwedge";
> pinctrl-0 = <&hdmi_ddc>;
> pinctrl-1 = <&hdmi_ddc_unwedge>;
>
> Note that this isn't added by default because some boards may choose
> to mux i2c5 for their DDC bus (if that is more tested for them).
ke it makes sense to use dw_hdmi's builtin I2C. Maybe eventually we
> can get HDCP negotiation working.
>
> Signed-off-by: Douglas Anderson
Reviewed-by: Sean Paul
> ---
>
> arch/arm/boot/dts/rk3288-veyron.dtsi | 11 ++-
> 1 file changed, 2 insertions(+),
t dpu_mdss_init(struct drm_device *dev)
> }
> dpu_mdss->mmio_len = resource_size(res);
>
> + ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
> + if (ret)
> + return ret;
> +
> mp = &dpu_mdss->mp;
> ret = msm_dss_parse_clock(pdev, mp);
> if (ret) {
> @@ -232,14 +273,14 @@ int dpu_mdss_init(struct drm_device *dev)
> irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
>dpu_mdss);
>
> + priv->mdss = &dpu_mdss->base;
> +
> pm_runtime_enable(dev->dev);
>
> pm_runtime_get_sync(dev->dev);
> dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
> pm_runtime_put_sync(dev->dev);
>
> - priv->mdss = &dpu_mdss->base;
> -
> return ret;
>
> irq_error:
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
On Sat, May 11, 2019 at 3:12 PM Laurent Pinchart
wrote:
>
> Hi Sean,
>
> Thank you for the patch.
>
Hey Laurent,
Thanks for looking!
> On Thu, May 02, 2019 at 03:49:46PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Everyone who implements connecto
y* handled, but missed
> clearing 'ret' resulting that hw_init() returned an error on these
> devices.
>
> Fixes: abccb9fe3267 drm/msm/a6xx: Add zap shader load
> Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 +
>
uot;(&drm_plane.state)"
so it's more clear what you're referring to here?
> + * and new_state. This is required because prepare and cleanup calls
> + * are performed on the new_state object, then to cleanup the old
> + * framebuffer, it needs to be placed inside the new_state object.
I'd change this bit to:
* This is required since cleanup for async commits is performed on
* the new state, rather than old state like for traditional commits.
* Since we want to give up the reference on the current (old) fb instead
* of our brand new one, swap them in the driver during the async commit.
> + *
>* FIXME:
>* - It only works for single plane updates
>* - Async Pageflips are not supported yet
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
From: Sean Paul
This patch adds a new drm helper library to help drivers implement
self refresh. Drivers choosing to use it will register crtcs and
will receive callbacks when it's time to enter or exit self refresh
mode.
In its current form, it has a timer which will trigger after a
d
From: Sean Paul
This patch adds atomic_enable and atomic_disable callbacks to the
encoder helpers. This will allow encoders to make informed decisions in
their start-up/shutdown based on the committed state.
Aside from the new hooks, this patch also introduces the new signature
for .atomic_
From: Sean Paul
This patch adds atomic variants for all of
pre_enable/enable/disable/post_disable bridge functions. These will be
called from the appropriate atomic helper functions. If the bridge
driver doesn't implement the atomic version of the function, we will
fall back to the va
From: Sean Paul
Now that we use the drm psr helpers, we no longer need to hand-roll our
atomic_commit_tail implementation. So use the helper
Changes in v2:
- None
Changes in v3:
- None
Link to v1:
https://patchwork.freedesktop.org/patch/msgid/20190228210939.83386-6-s...@poorly.run
Link to v2
From: Sean Paul
Instead of rolling our own implementation for tracking when PSR should
be [in]active, use the new self refresh helpers to do the heavy lifting.
Changes in v2:
- updated to reflect changes made in the helpers
Changes in v3:
- use the new atomic hooks to inspect crtc state instead
From: Sean Paul
Instead of fully disabling and re-enabling the vop on self refresh
transitions, only disable the active windows. This will speed up
self refresh exits substantially and is still a power-savings win.
This patch integrates portions of Zain's patch from here:
Reported-by: Dan Carpenter
> Signed-off-by: Jordan Crouse
Reviewed-by: Sean Paul
> ---
>
> drivers/gpu/drm/msm/msm_drv.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 87eae4
e.edid_firmware is deprecated, please use
> drm.edid_firmware intead.\n");
> + DRM_NOTE("drm_kms_firmware.edid_firmware is deprecated, please use
> drm.edid_firmware instead.\n");
>
> return __drm_set_edid_firmware_path(val);
> }
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
if (ret) {
> dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
> - return -EPROBE_DEFER;
> + ret = -EPROBE_DEFER;
> + goto err_unregister_host;
> }
>
> init_waitqueue_head(&dsi->irq_wait_queue);
>
> platform_set_drvdata(pdev, dsi);
>
> - return component_add(&pdev->dev, &mtk_dsi_component_ops);
> + ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
> + if (ret) {
> + ret = -EPROBE_DEFER;
> + goto err_unregister_host;
> + }
> +
> + return 0;
> +
> +err_unregister_host:
> + mipi_dsi_host_unregister(&dsi->host);
> + return ret;
> }
>
> static int mtk_dsi_remove(struct platform_device *pdev)
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
},
> + { .compatible = "mediatek,mt8183-dpi",
Do you need to add this compatible value to the dt binding? If you can do as CK
suggested, maybe you don't need this at all (and mt8183 can use the mt8173
compatible string in the dt).
Sean
> + .data = &mt8183_conf,
> + },
> { },
> };
>
> --
> 2.12.5
>
--
Sean Paul, Software Engineer, Google / Chromium OS
dri-devel wrote:
> > > > We've moved the tree to a shared gitlab tree, so that Sean can help out
> > > > with maintainer duties.
> > > >
> > > > Cc: Sean Paul
> > > > Signed-off-by: Rob Clark
> > > > ---
> > > &
On Wed, Feb 13, 2019 at 10:10:44AM -0500, Rob Clark via dri-devel wrote:
> We've moved the tree to a shared gitlab tree, so that Sean can help out
> with maintainer duties.
>
> Cc: Sean Paul
Acked-by: Sean Paul
> Signed-off-by: Rob Clark
> ---
> I can include this
Inline literal
> start-string without end-string.
>
> So, fix that by just removing the kerneldoc comments.
>
> Signed-off-by: Lyude Paul
Reviewed-by: Sean Paul
> Fixes: 022debad063e ("drm/atomic: Add drm_atomic_state->duplicated")
> Cc: Daniel Vetter
> ---
drivers/gpu/drm/panel/panel-seiko-43wvf1g.c| 18 ++--
> drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c| 66 ++-
> drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c| 27 +++---
> drivers/gpu/drm/panel/panel-simple.c | 22 +++--
> drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 16 ++--
> drivers/gpu/drm/panel/panel-truly-nt35597.c| 10 ++-
> 23 files changed, 375 insertions(+), 251 deletions(-)
--
Sean Paul, Software Engineer, Google / Chromium OS
t/dts/qcom-apq8064.dtsi | 5 +--
> > arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +--
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 20 +--
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_1
On Mon, Jan 28, 2019 at 10:56:29AM -0500, Sasha Levin wrote:
> From: Sean Paul
>
> [ Upstream commit c232e9f41b136c141df9938024e521191a7b910d ]
>
> Instead of always re-initializing the variables we need to clean up on
> out, move the re-initialization into the branch that
to know
what it's hung up on so we can avoid these refactor breakages.
Sean
>
> Sam
--
Sean Paul, Software Engineer, Google / Chromium OS
moval.
> >
> > Signed-off-by: Sam Ravnborg
> > Reviewed-by: Laurent Pinchart
> > Cc: Maarten Lankhorst
> > Cc: Maxime Ripard
> > Cc: Sean Paul
> > Cc: David Airlie
> > Cc: Daniel Vetter
>
> Merge the previous 5 patches from this series,
ence
> > > - lanes per dsi interface to 4 (two interfaces). Matches how tegra
> > > and pending rockchip dual-dsi handle (dual-)dsi lanes
> > > - spdx header instead of license boilerplate
> > >
> > > Signed-off-by: Nickey Yang
> > > Si
On Fri, Jan 18, 2019 at 12:58:10PM -0500, Sean Paul wrote:
> On Wed, Jan 9, 2019 at 1:59 AM Hsin-Yi, Wang wrote:
> >
> > Move mipi_dsi_dcs_set_display_off() from innolux_panel_disable()
> > to innolux_panel_unprepare(), so they are consistent with
> >
DP, DSI,
> - *HDMI etc.
> - * @intr: HW interrupt handle
> - * @mask: Returning the interrupt source MASK
> - * @return: 0 for success, otherwise failure
> - */
> - int (*get_valid_interrupts)(
> - struct dpu_hw_intr *intr,
> - uint32_t *mask);
> };
>
> /**
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
> ___
> Freedreno mailing list
> freedr...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
--
Sean Paul, Software Engineer, Google / Chromium OS
in the next atomic check
> - * @plane: Pointer to DRM plane object
> - * @enable: Boolean to set/unset the flag
> - */
> -void dpu_plane_set_revalidate(struct drm_plane *plane, bool enable);
> -
> #endif /* _DPU_PLANE_H_ */
> --
> The Qualcomm Innovation Center, Inc. is a member of
oject
>
> ___
> Freedreno mailing list
> freedr...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
--
Sean Paul, Software Engineer, Google / Chromium OS
cc/0x10c
> mark_lock+0xbe0/0xe24
> __lock_acquire+0x4cc/0x2708
> lock_acquire+0x244/0x360
> _raw_spin_lock+0x64/0xa0
> handle_level_irq+0x34/0x26c
> generic_handle_irq+0x44/0x5c
> dpu_mdss_irq+0x64/0xec
> irq_forced_thread_fn+0x58/0x9c
> irq_thread+0x120/0x1dc
>
ds to be in cmd mode to be able to send commands
> (e.g. mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode()),
> so we need these functions to be called after the switch to cmd mode happens,
> i.e. in innolux_panel_unprepare.
>
>
> Signed-off-by: Hsin-Yi,
ff-by: Maxime Ripard
Aside from the wakeup change mentioned in patch 8,
Acked-by: Sean Paul
> ---
> drivers/gpu/drm/bridge/Kconfig| 1 +-
> drivers/gpu/drm/bridge/cdns-dsi.c | 485 +++
> drivers/phy/cadence/cdns-dphy.c | 2 +-
> 3 files chang
evm_clk_get(&pdev->dev, "pll_ref");
> + if (IS_ERR(dphy->pll_ref_clk))
> + return PTR_ERR(dphy->pll_ref_clk);
> +
> + if (dphy->ops->probe) {
> + ret = dphy->ops->probe(dphy);
> + if (ret)
>
id(struct drm_bridge *bridge,
> if ((mode->hdisplay * bpp) % 32)
> return MODE_H_ILLEGAL;
>
> - nlanes = output->dev->lanes;
> -
> - ret = cdns_dsi_mode2cfg(dsi, mode, &dsi_cfg, &dphy_cfg, true);
> + ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, &dphy_cfg, true);
> if (ret)
> - return MODE_CLOCK_RANGE;
> + return MODE_BAD;
>
> return MODE_OK;
> }
> @@ -990,7 +1030,7 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
> *bridge)
> bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
> nlanes = output->dev->lanes;
>
> - WARN_ON_ONCE(cdns_dsi_mode2cfg(dsi, mode, &dsi_cfg, &dphy_cfg, false));
> + WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, &dphy_cfg,
> false));
>
> cdns_dsi_hs_init(dsi, &dphy_cfg);
> cdns_dsi_init_link(dsi);
> --
> git-series 0.9.1
--
Sean Paul, Software Engineer, Google / Chromium OS
On Tue, Dec 18, 2018 at 05:06:38PM +0530, Jagan Teki wrote:
> On Sat, Dec 15, 2018 at 3:32 AM Sean Paul wrote:
> >
> > On Sat, Dec 15, 2018 at 02:11:01AM +0530, Jagan Teki wrote:
> > > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
> > &
+
> + ret = drm_panel_add(&ctx->panel);
> + if (ret < 0)
> + goto put_backlight;
> +
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->lanes = 4;
> +
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0)
> + goto panel_remove;
> +
> + return ret;
> +
> +panel_remove:
> + drm_panel_remove(&ctx->panel);
> +put_backlight:
> + if (ctx->backlight)
> + put_device(&ctx->backlight->dev);
> +
> + return ret;
> +}
> +
> +static int feiyang_dsi_remove(struct mipi_dsi_device *dsi)
> +{
> + struct feiyang *ctx = mipi_dsi_get_drvdata(dsi);
> +
> + mipi_dsi_detach(dsi);
> + drm_panel_remove(&ctx->panel);
> +
> + if (ctx->backlight)
> + put_device(&ctx->backlight->dev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id feiyang_of_match[] = {
> + { .compatible = "feiyang,fy07024di26a30d", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, feiyang_of_match);
> +
> +static struct mipi_dsi_driver feiyang_driver = {
> + .probe = feiyang_dsi_probe,
> + .remove = feiyang_dsi_remove,
> + .driver = {
> + .name = "feiyang-fy07024di26a30d",
> + .of_match_table = feiyang_of_match,
> + },
> +};
> +module_mipi_dsi_driver(feiyang_driver);
> +
> +MODULE_AUTHOR("Jagan Teki ");
> +MODULE_DESCRIPTION("Feiyang FY07024DI26A30-D MIPI-DSI LCD panel");
> +MODULE_LICENSE("GPL");
> --
> 2.18.0.321.gffc6fa0e3
>
--
Sean Paul, Software Engineer, Google / Chromium OS
_FMT(RGBA,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
On Fri, Dec 14, 2018 at 04:35:11PM +0530, Jagan Teki wrote:
> On Fri, Dec 14, 2018 at 1:25 AM Sean Paul wrote:
> >
> > On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote:
> > > On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
> > > >
> > &g
On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote:
> On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote:
> > > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
> > &
amp;ctx->panel);
> + if (ret < 0)
> + goto put_backlight;
> +
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->lanes = 4;
> +
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0)
> + goto panel_remove;
> +
> + return ret;
> +
> +panel_remove:
> + drm_panel_remove(&ctx->panel);
> +put_backlight:
> + if (ctx->backlight)
> + put_device(&ctx->backlight->dev);
> +
> + return ret;
> +}
> +
> +static int feiyang_dsi_remove(struct mipi_dsi_device *dsi)
> +{
> + struct feiyang *ctx = mipi_dsi_get_drvdata(dsi);
> +
> + mipi_dsi_detach(dsi);
> + drm_panel_remove(&ctx->panel);
> +
> + if (ctx->backlight)
> + put_device(&ctx->backlight->dev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id feiyang_of_match[] = {
> + { .compatible = "feiyang,fy07024di26a30d", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, feiyang_of_match);
> +
> +static struct mipi_dsi_driver feiyang_driver = {
> + .probe = feiyang_dsi_probe,
> + .remove = feiyang_dsi_remove,
> + .driver = {
> + .name = "feiyang-fy07024di26a30d",
> + .of_match_table = feiyang_of_match,
> + },
> +};
> +module_mipi_dsi_driver(feiyang_driver);
> +
> +MODULE_AUTHOR("Jagan Teki ");
> +MODULE_DESCRIPTION("Feiyang FY07024DI26A30-D MIPI-DSI LCD panel");
> +MODULE_LICENSE("GPL");
> --
> 2.18.0.321.gffc6fa0e3
>
--
Sean Paul, Software Engineer, Google / Chromium OS
n = dpu_crtc->enabled;
> dpu_crtc->enabled = false;
>
> + if (crtc_en && dpu_crtc->vblank_requested)
> + _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false);
> +
> if (atomic_read(&dpu_crtc->frame_pending)) {
> trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
>atomic_read(&dpu_crtc->frame_pending));
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
--
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
From: Sean Paul
Now that we don't have any event handlers, remove dpu_power_handle!
Changes in v2:
- None
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 --
driver
_dpcd_writeb() and dp_dpcd_readb() to detect when the aux channel
> was up. In theory that would let me detect _exactly_ when I could
> continue and do link training. Unfortunately even if I did an aux
> transfer w/out waiting I couldn't see any errors. Possibly I could
> keep
> > > > to
> > > > > make the debugfs nodes for atomic instead of checking DRIVER_ATOMIC,
> > > > > as
> > > > > the former isn't an accurate representation of whether or not the
> > > > > driver
> > >
On Fri, Jun 22, 2018 at 7:01 AM Al Viro wrote:
>
> On Fri, Jun 22, 2018 at 12:00:14PM +0200, Christoph Hellwig wrote:
> > And a version with select() also covered:
>
> For fuck sake, if you want vfs_poll() inlined, *make* *it* *inlined*.
> Is there any reason for not doing that other than EXPORT_S
t; + *
> + * If it doesn't exist, then allocate a new notifier struct and return a
> + * pointer to that new struct.
You might also want to cover the case where you have multiple named notifiers
for the same device. It looks like it just grabs the first one?
Sean
> + *
> + * Return NULL if the memory could not be allocated.
> + */
> +static inline struct cec_notifier *cec_notifier_get(struct device *dev)
> +{
> + return cec_notifier_get_conn(dev, NULL);
> +}
> +
> +/**
> * cec_notifier_phys_addr_invalidate() - set the physical address to INVALID
> *
> * @n: the CEC notifier
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
On Fri, May 18, 2018 at 10:52:17AM +0200, Heiko Stuebner wrote:
> Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris:
> > On Thu, May 17, 2018 at 6:41 PM, hl wrote:
> > > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
> > >> On Thu, May 17, 2018
CYC 0x8000
>
> +/* register CM_VID_CTRL */
> +#define LANE_VID_REF_CYC(x)(((x) & (BIT(24) - 1)) << 0)
> +#define NMVID_MEAS_TOLERANCE(x)(((x) & 0xf) << 24)
> +
> +/* register DP_TX_PHY_CONFIG_REG */
> +#define DP_TX_PHY_TRAINING_ENABLE(x) ((x) & 1)
> +#define DP_TX_PHY_TRAINING_TYPE_PRBS7 (0 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_TPS1 (1 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_TPS2 (2 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_TPS3 (3 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_TPS4 (4 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_PLTPAT (5 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_D10_2 (6 << 1)
> +#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT (8 << 1)
> +#define DP_TX_PHY_TRAINING_PATTERN(x) ((x) << 1)
> +#define DP_TX_PHY_SCRAMBLER_BYPASS(x) (((x) & 1) << 5)
> +#define DP_TX_PHY_ENCODER_BYPASS(x)(((x) & 1) << 6)
> +#define DP_TX_PHY_SKEW_BYPASS(x) (((x) & 1) << 7)
> +#define DP_TX_PHY_DISPARITY_RST(x) (((x) & 1) << 8)
> +#define DP_TX_PHY_LANE0_SKEW(x)(((x) & 7) << 9)
> +#define DP_TX_PHY_LANE1_SKEW(x)(((x) & 7) << 12)
> +#define DP_TX_PHY_LANE2_SKEW(x)(((x) & 7) << 15)
> +#define DP_TX_PHY_LANE3_SKEW(x)(((x) & 7) << 18)
> +#define DP_TX_PHY_10BIT_ENABLE(x) (((x) & 1) << 21)
> +
> +/* register DP_FRAMER_GLOBAL_CONFIG */
> +#define NUM_LANES(x) ((x) & 3)
> +#define SST_MODE (0 << 2)
> +#define RG_EN (0 << 4)
> +#define GLOBAL_EN BIT(3)
> +#define NO_VIDEO BIT(5)
> +#define ENC_RST_DISBIT(6)
> +#define WR_VHSYNC_FALL BIT(7)
> +
> enum voltage_swing_level {
> VOLTAGE_LEVEL_0,
> VOLTAGE_LEVEL_1,
> @@ -476,6 +510,7 @@ int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8
> lanes, bool flip);
> int cdn_dp_event_config(struct cdn_dp_device *dp);
> u32 cdn_dp_get_event(struct cdn_dp_device *dp);
> int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
> +int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
> ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
> u8 *data, u16 len);
> ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
> @@ -489,4 +524,5 @@ int cdn_dp_config_video(struct cdn_dp_device *dp);
> int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
> int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
> int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
> +int cdn_dp_software_train_link(struct cdn_dp_device *dp);
> #endif /* _CDN_DP_REG_H */
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
> + * fail, keep firmware training as a fallback if sw training fails.
> + */
> + ret = cdn_dp_software_train_link(dp);
> + if (ret) {
> + DRM_DEV_ERROR(dp->dev,
> + "Failed to do software training %d\n", ret);
> + goto do_fw_training;
> + }
> + ret = cdn_dp_reg_write(dp, SOURCE_HDTX_CAR, 0xf);
> + if (ret) {
> + DRM_DEV_ERROR(dp->dev,
> + "Failed to write SOURCE_HDTX_CAR register %d\n", ret);
> + goto do_fw_training;
> + }
> + dp->use_fw_training = false;
> + return 0;
> +
> +do_fw_training:
> + dp->use_fw_training = true;
> + DRM_DEV_DEBUG_KMS(dp->dev, "use fw training\n");
> ret = cdn_dp_training_start(dp);
> if (ret) {
> DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret);
> @@ -623,7 +650,7 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
>
> DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
> dp->link.num_lanes);
> - return ret;
> + return 0;
> }
>
> int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
>
/snip
--
Sean Paul, Software Engineer, Google / Chromium OS
> +
> + {{ 0x21, 0x00 },
> + { 0x12, 0x15 },
> + { 0x02, 0x22 },
> + {0,0 } },
> +
> + {{ 0x15, 0x00 },
> + { 0x00, 0x15 },
> + {0,0 },
> + {0,0 } },
> +};
> +
/snip
--
Sean Paul, Software Engineer, Google / Chromium OS
VOLTAGE_LEVEL_0,
> VOLTAGE_LEVEL_1,
> @@ -476,6 +510,7 @@ int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8
> lanes, bool flip);
> int cdn_dp_event_config(struct cdn_dp_device *dp);
> u32 cdn_dp_get_event(struct cdn_dp_device *dp);
> int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
> +int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
> ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
> u8 *data, u16 len);
> ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
> @@ -489,4 +524,5 @@ int cdn_dp_config_video(struct cdn_dp_device *dp);
> int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
> int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
> int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
> +int cdn_dp_software_train_link(struct cdn_dp_device *dp);
> #endif /* _CDN_DP_REG_H */
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
ed for each port the phy provides.
>The sub-node name is used to identify dp or usb3 port,
>and shall be the following entries:
> --
> 2.7.4
>
--
Sean Paul, Software Engineer, Google / Chromium OS
onst struct rockchip_usb3phy_port_cfg *port_cfgs;
> + /* mutex to protect access to individual PHYs */
> + struct mutex lock;
> + struct phy_config config[3][4];
> + u8 need_software_training;
I thought we decided to always do sw training and then fallback to fw training.
I
uang
FTR, I've already done one pass at [1]. All of those nits look fixed, so
Reviewed-by: Sean Paul
[1]-
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/985572
> ---
>
> Changes in v2:
> - update patch following Enric suggest
>
&g
IFT;
> > @@ -77,7 +77,6 @@ static int vgem_gem_fault(struct vm_fault *vmf)
> > if (page_offset > num_pages)
> > return VM_FAULT_SIGBUS;
> >
> > - ret = -ENOENT;
> > mutex_lock(&obj->pages_lock);
> > if (obj-&
DRM_ERROR("Unknown media bus format %d\n", bus_format);
> break;
> }
> + } else {
> + /* Default to 24bit if no connector found. */
> + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
> }
On Fri, Apr 20, 2018 at 02:59:59PM -0400, Sean Paul wrote:
> edid should be freed once it's finished being used.
>
> Fixes: 56fe8b6f4991 ("drm/bridge: Add RGB to VGA bridge support")
> Cc: Rob Herring
> Cc: Sean Paul
> Cc: Maxime Ripard
> Cc: Archit Taneja
edid should be freed once it's finished being used.
Fixes: 56fe8b6f4991 ("drm/bridge: Add RGB to VGA bridge support")
Cc: Rob Herring
Cc: Sean Paul
Cc: Maxime Ripard
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: # v4.9+
Signed-off-by: Sean Paul
---
drivers
JFYI, in future, if someone makes a suggestion on how to fix a bug, it's good
practice to add a Suggested-by tag to give credit.
Reviewed-by: Sean Paul
> Signed-off-by: Emil Lundmark
> ---
> drivers/gpu/drm/udl/udl_fb.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deleti
Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_atomic.c | 25 -
1 file
swap_state to avoid abandoned events on disable
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_atomic.c | 153 +--
drivers/gpu/drm/msm/msm_drv.c| 1 -
drivers/gpu/drm/msm/msm_drv.h| 4 -
3 files changed, 42 insertions(+), 116 deletions(-)
diff --git
Now that all of the msm-specific goo is tucked safely away we can switch
over to using the atomic helper commit directly. \o/
Changes in v2:
- None
Cc: Abhinav Kumar
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_atomic.c | 120 +--
drivers/gpu/drm/msm
Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).
Changes in v2:
- None
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 +
1 file ch
Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
drivers/gpu/drm/msm
n do whatever it wants
- * with the ->state ptr. On ->atomic_state_clear() the ->state ptr
- * is kfree'd and set back to NULL.
+ * with the ->state ptr.
*/
struct msm_kms_state {
- struct drm_atomic_state base;
+ struct drm_private_state base;
void *state;
};
-#define to_kms_state(x) container_of(x, struct msm_kms_state, base)
+
+/**
+ * Extracts the msm_kms_state from either an atomic state, or the current
+ * device. One or the other might be desirable depending on whether you want
the
+ * currently configured msm_kms_state (from_dev), or you would like the state
+ * which is about to be applied (from_atomic).
+ */
+struct msm_kms_state *msm_kms_state_from_dev(struct drm_device *dev);
+struct msm_kms_state *msm_kms_state_from_atomic(struct drm_atomic_state
*state);
static inline void msm_kms_init(struct msm_kms *kms,
const struct msm_kms_funcs *funcs)
--
Sean Paul, Software Engineer, Google / Chromium OS
t; * Frees any pages and buffers associated with the given entry.
> */
> -static void drm_cleanup_buf_error(struct drm_device * dev,
> - struct drm_buf_entry * entry)
> +static void drm_cleanup_buf_error(struct drm_device *dev,
> + struct drm_buf_entry *entry)
> {
> int i;
>
> --
> 2.16.2
>
--
Sean Paul, Software Engineer, Google / Chromium OS
driver.
>
Thanks for sending these patches!
With Archit and Daniel's comments addressed, feel free to add my
Reviewed-by: Sean Paul
>
> Alexandru M Stan (2):
> dt-bindings: analogix-dp: Add backlight-pwm-passthru
> drm/bridge: analogix: Enable EDP_BACKLIGHT_FREQ_PWM_PIN_P
support for Sitronix ST7735R display panels"
> depends on DRM_TINYDRM && SPI
> + depends on BACKLIGHT_CLASS_DEVICE
> select TINYDRM_MIPI_DBI
> help
> DRM driver Sitronix ST7735R with one of the following LCDs:
> --
> 2.9.0
>
--
Sean Paul, Software Engineer, Google / Chromium OS
On Fri, Feb 23, 2018 at 01:15:54PM -0500, Rob Clark wrote:
> On Fri, Feb 23, 2018 at 11:30 AM, Sean Paul wrote:
> > On Fri, Feb 23, 2018 at 08:17:54AM -0500, Rob Clark wrote:
> >> In a way, based on the original writeback patch from Jilai Wang, but a
> >> lot ha
On Fri, Feb 23, 2018 at 04:48:58PM +, Liviu Dudau wrote:
> On Fri, Feb 23, 2018 at 11:43:29AM -0500, Sean Paul wrote:
> > On Fri, Feb 23, 2018 at 11:25:11AM -0500, Rob Clark wrote:
> > > On Fri, Feb 23, 2018 at 10:59 AM, Sean Paul wrote:
> > > >
> > >
On Fri, Feb 23, 2018 at 11:25:11AM -0500, Rob Clark wrote:
> On Fri, Feb 23, 2018 at 10:59 AM, Sean Paul wrote:
> >
> > Have we considered hiding writeback behind a client cap instead?
>
> It is kinda *almost* unneeded, since the connector reports itself as
> disconnected
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