On Thu, Apr 15, 2021 at 2:58 AM simba.hsu
wrote:
>
> This path makes auto-update available when IC's status is
> Recovery mode.
>
> Signed-off-by: simba@raydium.corp-partner.google.com
> Change-Id: I5ae54896a201b949eba7514500a7e75574f5726b
> ---
> drivers/input/touchscreen/raydium_i2c_ts.c |
Thanks Victor and Ulf!
On Tue, Oct 27, 2020 at 7:42 AM Ulf Hansson wrote:
>
> On Tue, 27 Oct 2020 at 09:46, Victor Ding wrote:
> >
> > From: Raul E Rangel
> >
> > This change will allow platform designers better control over signal
> > integrity by allowing them to tune the HS200 and HS400 driv
On Tue, Sep 1, 2020 at 4:54 AM Adrian Hunter wrote:
>
> On 24/08/20 9:21 pm, Raul E Rangel wrote:
> > SDHCI presets are not currently used for eMMC HS/HS200/HS400, but are
> > used for DDR52. The HS400 retuning sequence is:
> >
> > HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
> >
> > Thi
> >
> > Should we pull that in too, or is it fine to wait for the next merge?
>
> It depends on wha tyou want to do. I can drop this now and add both
> later, or just be "bug compatible" with Linus's tree until this patch
> gets merged into it, and then I can take it.
>
> Your call...
>
The patch
On Sat, Aug 29, 2020 at 1:48 AM Pavel Machek wrote:
>
> On Thu 2020-08-27 13:52:22, Raul E Rangel wrote:
> > The i8042_mutex must be held by writers of the AUX and KBD ports, as
> > well as users of i8042_command. There were a lot of users of
> > i8042_command that were not calling i8042_lock_chip
On Thu, Aug 27, 2020 at 2:12 PM Andy Shevchenko
wrote:
>
> On Thu, Aug 27, 2020 at 10:52 PM Raul E Rangel wrote:
> >
> > The i8042_mutex must be held by writers of the AUX and KBD ports, as
> > well as users of i8042_command. There were a lot of users of
> > i8042_command that were not calling i8
On Fri, Aug 14, 2020 at 9:39 PM Gwendal Grignou wrote:
>
> In ftrace, add more fields to the cros_ec command event:
> - Add size of commands to check if they are properly set.
> - Add offset (in case an EC is cascaded being another EC),
> to allow proper command output
>
> With:
> echo 1 > events/
Thanks for clarifying Dmitry. I'll get a patch pushed up next week.
On Wed, Aug 12, 2020 at 7:21 PM Dmitry Torokhov
wrote:
>
> On Thu, Aug 06, 2020 at 09:28:41AM -0600, Raul Rangel wrote:
> > >
> > > <- atkbd_event_work->atkbd_set_leds
> > > [KB recv
I'm debugging a resume issue on one of our devices using the v5.4
kernel. The device has a PS/2 atkbd and a PS/2 touchpad. It looks like
PS/2 commands are getting intermingled with i8042 commands. This
results in our keyboard controller thinking it got some invalid data.
This usually happens 1 out
Hey everyone,
So it looks like this was a red herring. We were getting spurious
interrupts which I suspect caused the console code to get called in
some critical section. Once we fixed the spurious interrupts we no
longer see the issue. Sorry for the noise.
Thanks,
Raul
On Thu, Jul 9, 2020 at 7:2
We are trying an S3 suspend stress test and occasionally while
entering S3 we get a console deadlock. Is this a known issue? I'm not
really sure why a probe would be happening while suspending.
The kernel command line is `console=ttyS0` and kernel 5.4.39.
Here is the log:
[ 278.885831] leds mmc
On Fri, Oct 11, 2019 at 7:39 AM Enric Balletbo i Serra
wrote:
>
> There are some EC commands that are not included yet as trace commands,
> in order to get all the traces for the all supported commands match the
> commands accordingly.
>
> Note that a change, adding or removing an EC command, shou
On Mon, Sep 23, 2019 at 03:31:59PM +0300, Adrian Hunter wrote:
> Should have Acked this ages ago, sorry :-(
>
> Acked-by: Adrian Hunter
Thanks, and no worries :)
Ulf, The patch set is ready to merge now :)
Pinging the patch set to make sure it's not forgotten :)
Thanks
On Mon, Aug 26, 2019 at 02:24:14PM -0700, Stephen Boyd wrote:
> >
> > ---8<---
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index c0990703ce54..f42a803fb11a 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -3737,6 +3737,37 @@ static const struct clk_ops clk_nodrv
On Wed, Aug 07, 2019 at 09:10:10PM +, Shirley Her (SC) wrote:
> Fix data read/write error in HS200 mode due to chip DLL lock phase shift
> +static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
> +{
> + ktime_t timeout;
> + u32 scratch32;
> +
> + usleep_range(5000, 6000)
On Fri, Aug 02, 2019 at 07:58:20AM +0300, Adrian Hunter wrote:
>
> You seem not to have answered to my suggestion for a change to sdhci_reinit()
> here:
>
>
> https://lore.kernel.org/lkml/fcdf6cc4-2729-abe2-85c8-b0d04901c...@intel.com/
>
I thought I answered it here:
https://lore.kernel
On Wed, Jun 19, 2019 at 08:56:25AM -0600, Raul Rangel wrote:
> Your patch looks good. I tried it out and got over 57k insertion/removal
> iterations. Do you want me to send out your patch, or do you want to do
> it?
>
> Just to recap, the patch you proposed + the AMD SDHCI spe
On Thu, Aug 01, 2019 at 03:30:53PM +0200, Enric Balletbo i Serra wrote:
> Got it. I don't think this is a "kernel" way to do it. Also, I don't see a big
> value on doing this.
Code generation sounds great, but it makes finding and looking at the
source file difficult unless you have a build. It
On Wed, Jun 19, 2019 at 07:09:17PM +0200, Greg Kroah-Hartman wrote:
> On Wed, Jun 19, 2019 at 10:46:25AM -0600, Raul Rangel wrote:
> > On Tue, May 14, 2019 at 11:19:34AM +0200, Greg Kroah-Hartman wrote:
> > > On Mon, May 13, 2019 at 11:55:18AM -0600, Raul E Rangel wrote:
> &g
On Tue, May 14, 2019 at 11:19:34AM +0200, Greg Kroah-Hartman wrote:
> On Mon, May 13, 2019 at 11:55:18AM -0600, Raul E Rangel wrote:
> > I think we should cherry-pick 41e3efd07d5a02c80f503e29d755aa1bbb4245de
> > https://lore.kernel.org/patchwork/patch/856512/ into 4.14. It fixes a
> > potential res
On Tue, Jun 11, 2019 at 01:30:55PM +0300, Adrian Hunter wrote:
> Does the following work?
>
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 0cd5f2ce98df..f672171246b0 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -341,8 +341,19 @@ stati
On Wed, Jun 12, 2019 at 04:09:47PM +0300, Adrian Hunter wrote:
> On 10/06/19 9:53 PM, Raul E Rangel wrote:
> > The O2 controller supports 8-bit EMMC access. mmc_select_bus_width()
> > will be used to determine if the MMC supports 8-bit or 4-bit access.
>
> The problem is that the bit indicates a h
On Wed, Jun 12, 2019 at 03:36:25PM +0200, Ulf Hansson wrote:
> On Mon, 10 Jun 2019 at 20:54, Raul E Rangel wrote:
> >
> > sdhci_send_tuning uses mmc->ios.bus_width to determine the block size.
> > Without this patch the block size would be set incorrectly when the
> > bus_width == 8 which results
On Mon, Jun 10, 2019 at 06:17:31PM +0200, Ulf Hansson wrote:
> + Adrian
>
> On Fri, 7 Jun 2019 at 18:05, Raul Rangel wrote:
> >
> > On Tue, May 28, 2019 at 09:38:20AM +0200, Ulf Hansson wrote:
> > > On Wed, 1 May 2019 at 19:55, Raul E Rangel wrote:
> >
On Tue, May 28, 2019 at 09:38:20AM +0200, Ulf Hansson wrote:
> On Wed, 1 May 2019 at 19:55, Raul E Rangel wrote:
First off, thanks for the review.
> >
> > There is a race condition between resetting the SDHCI controller and
> > disconnecting the card.
> >
> > For example:
> > 0) Card is connecte
On Tue, May 28, 2019 at 09:41:07AM +0200, Ulf Hansson wrote:
> On Wed, 1 May 2019 at 19:55, Raul E Rangel wrote:
> >
> > AMD SDHC 0x7906 requires a hard reset to clear all internal state.
> > Otherwise it can get into a bad state where the DATA lines are always
> > read as zeros.
> >
> > This chan
> > Errm. I think we need to fix that problem instead of working around it.
> So mmc_request_fn already has a null check, it was just missing on
> mmc_init_request.
>
So I got 189650 random connect/disconnect iterations over the weekend
with these patches. I think they are fine. I'm going to send
On Wed, May 08, 2019 at 11:04:56PM -0700, Christoph Hellwig wrote:
> On Wed, May 08, 2019 at 12:58:32PM -0600, Raul E Rangel wrote:
> > It is possible for queuedata to be cleared in mmc_cleanup_queue before
> > the request has been started.
>
> Errm. I think we need to fix that problem instead of
On Fri, May 03, 2019 at 09:12:24AM -0600, Raul Rangel wrote:
> On Wed, May 01, 2019 at 11:54:56AM -0600, Raul E Rangel wrote:
> > I am running into a kernel panic. A task gets stuck for more than 120
> > seconds. I keep seeing blkdev_close in the stack trace, so maybe I'm not
&
On Wed, May 01, 2019 at 11:54:56AM -0600, Raul E Rangel wrote:
> I am running into a kernel panic. A task gets stuck for more than 120
> seconds. I keep seeing blkdev_close in the stack trace, so maybe I'm not
> calling something correctly?
>
> Here is the panic:
> https://privatebin.net/?8ec48c1
Ou Thu, May 02, 2019 at 09:32:16AM +0300, Adrian Hunter wrote:
Gene or Chris,
Can you sign off on the patch.
Thanks,
Raul
> Cc: some AMD people
>
> On 1/05/19 8:54 PM, Raul E Rangel wrote:
> > AMD SDHC 0x7906 requires a hard reset to clear all internal state.
> > Otherwise it can get into a bad
On Thu, Apr 18, 2019 at 06:20:26AM +, Avri Altman wrote:
> >
> > The SD Physical Layer Spec says the following: Since the SD Memory Card
> > shall support at least the two bus modes 1-bit or 4-bit width, then any SD
> > Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101").
> >
> > This
On Tue, Apr 23, 2019 at 08:29:15AM +0200, Ulf Hansson wrote:
> On Tue, 16 Apr 2019 at 20:33, Raul E Rangel wrote:
> >
> > I am not able to make a single event class for all these registers. They
> > all have different struct sizes and different printf formats.
> >
> > Thanks for the reviews!
> >
>
On Thu, Apr 18, 2019 at 09:24:16AM +0300, Adrian Hunter wrote:
> On 12/04/19 5:50 PM, Raul Rangel wrote:
> > On Fri, Apr 12, 2019 at 09:26:44AM +0300, Adrian Hunter wrote:
> >> On 12/04/19 1:08 AM, Raul E Rangel wrote:
> >>> I was debugging a SDHC hardware
On Fri, Apr 12, 2019 at 03:04:38PM -0400, Steven Rostedt wrote:
> On Fri, 12 Apr 2019 12:49:44 -0600
> Raul E Rangel wrote:
>
> > +#define ec_cmds \
> > + {EC_CMD_PROTO_VERSION, "PROTO_VERSION"}, \
> > + {EC_CMD_HELLO, "HELLO"}, \
> > + {EC_CMD_GET_VERSION, "GET_VERSION"}, \
> > + {EC_CMD
On Thu, Apr 11, 2019 at 06:39:34PM -0400, Steven Rostedt wrote:
> On Thu, 11 Apr 2019 16:08:19 -0600
> Raul E Rangel wrote:
>
> > This is a hybrid method that combines the functionality of
> > trace_print_flags_seq and trace_print_symbols_seq. It supports printing
> > bit fields, enum fields, and
On Fri, Apr 12, 2019 at 09:26:44AM +0300, Adrian Hunter wrote:
> On 12/04/19 1:08 AM, Raul E Rangel wrote:
> > I was debugging a SDHC hardware bug and got tired of having to
> > translate the register values by hand. This patch set makes it so all
> > SDHC register read and write operations can be
On Thu, Apr 11, 2019 at 11:55:40PM +0200, Enric Balletbo Serra wrote:
> Hi,
>
> Many thanks for sending this patch upstream. Looks really interesting.
> Some few comments below ...
>
> Please prefix the patch with "chrome/platform: cros_ec_proto: ..."
>
> Missatge de Raul E Rangel del dia dc.,
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