previous mail.
Besides, this patch won't solve all the problem, if you
don't disable the size_aligned of the iova driver or
there would be a gap between the plane 0 and plane 1.
This patch is used for showing the problem we met not
for merging.
Signed-off-by: Randy Li
---
drivers/me
From: Randy Li
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 84f14b132e8f
I don't care, I don't want to store buffers for a session.
I just want to use it to verify the FFmpeg.
I want the memory region !!!
It can save more time if those data are prepared in userspace.
Signed-off-by: Randy Li
---
drivers/staging/rockchip-mpp/mpp_dev_common.c | 3 +--
drive
From: Randy Li
It is based on the vendor driver sent to mail list before.
Only MPEG2 video for VDPU2 works. And it need a patch to
fill the QP table.
I have finished the register table of the rkvdec and rk hevc
decoder. But I can't feed its proper input stream, I will
talk the reason
ink I need to do some work at v4l2 core.
Randy Li (6):
arm64: dts: rockchip: add power domain to iommu
staging: video: rockchip: add v4l2 decoder
[TEST]: rockchip: mpp: support qptable
staging: video: rockchip: add video codec
arm64: dts: rockchip: boost clocks for rk3328
arm64: dts: roc
From: Randy Li
Signed-off-by: Randy Li
---
drivers/staging/Kconfig | 2 ++
drivers/staging/Makefile | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index c0901b96cfe4..5f84035e2a89 100644
--- a/drivers/staging/Kconfig
+++ b/drivers
On 1/22/19 2:26 PM, Alexandre Courbot wrote:
Documents the protocol that user-space should follow when
communicating with stateless video decoders.
The stateless video decoding API makes use of the new request and tags
APIs. While it has been implemented with the Cedrus driver so far, it
shoul
format and
rebased.
Cc: Daniel Stone
Cc: Ville Syrjälä
Signed-off-by: Randy Li
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/drm_fourcc.c | 9 +
include/uapi/drm/drm_fourcc.h | 21 +
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b
for that
driver is sent before.
Randy Li (2):
drm/fourcc: Add new P010, P016 video format
drm/fourcc: add a 10bits fully packed variant of NV12
drivers/gpu/drm/drm_fourcc.c | 13 +
include/uapi/drm/drm_fourcc.h | 29 +
2 files changed, 42 insertions(+)
--
2.20.1
This pixel format is a fully packed and 10bits variant of NV12.
A luma pixel would take 10bits in memory, without any
filled bits between pixels in a stride.
Signed-off-by: Randy Li
---
drivers/gpu/drm/drm_fourcc.c | 4
include/uapi/drm/drm_fourcc.h | 8
2 files changed, 12
On 12/12/18 8:51 PM, Paul Kocialkowski wrote:
Hi,
On Wed, 2018-12-05 at 21:59 +0100, Jernej Škrabec wrote:
+
+#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01
+#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER 0x02
+#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR0x03
+
+#define V4L2_
ff-by: Randy Li
---
.../boot/dts/rockchip/rk3399-sapphire.dtsi| 29
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 68 +--
2 files changed, 90 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
b/arch/arm64/boot/dts/rockchip/r
Signed-off-by: Randy Li
---
drivers/staging/rockchip-mpp/Kconfig | 52 +
drivers/staging/rockchip-mpp/Makefile | 16 +
drivers/staging/rockchip-mpp/mpp_debug.h | 87 ++
drivers/staging/rockchip-mpp/mpp_dev_common.c | 971 ++
drivers/staging/rockchip-mpp
Signed-off-by: Randy Li
---
drivers/staging/Kconfig | 2 ++
drivers/staging/Makefile | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e4f608815c05..81634dd0a283 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
Fixing those deprecated function from vendor kernel.
Removing those features don't exist in upstream kernel.
Signed-off-by: Randy Li
---
drivers/staging/rockchip-mpp/mpp_dev_common.c | 12 ++--
drivers/staging/rockchip-mpp/mpp_dev_common.h | 2 +-
drivers/staging/rockchi
ould attend the FOSDEM 2019, if you have any problem, I think you can
catch me easily there.
Randy Li (4):
staging: video: rockchip: video codec for vendor API
staging: video: rockchip: fixup for upstream
staging: video: rockchip: add video codec
arm64: dts: rockchip: add video codec
IOMMU device won't work without power unless PMU
can't turn it off.
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6c
Video codec won't work properly with a clock too low nor
too high. We need to export them, allowing the device
tree to assign a suitable clocks for them.
Signed-off-by: Randy Li
---
drivers/clk/rockchip/clk-rk3399.c | 5 +++--
include/dt-bindings/clock/rk3399-cru.h | 2 ++
2 files ch
ernel for rockchip, network, eMMC,
USB and VOP work much worse and slow than the vendor kernel. I think the
video codec driver would be a good example to verify the other drivers.
Randy Li (3):
clk: rockchip: add video clk parents for rk3399
arm64: dts: rockchip: add power domain to iommu r
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Signed-off-by: Caesar Wang
Signed-off-by: Jeffy Chen
Signed-off-b
This pixel format is a fully packed and 10bits variant of NV12.
A luma pixel would take 10bits in memory, without any
filled bits between pixels in a stride. The color gamut
follows the BT.2020 standard.
Signed-off-by: Randy Li
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm
Those pins would be used by many boards.
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 87 +++-
1 file changed, 73 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399
Those pins would be used by many boards.
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 97 +++-
1 file changed, 83 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399
On 05/22/2018 05:26 PM, Maarten Lankhorst wrote:
Op 20-05-18 om 19:17 schreef Randy Li:
This pixel format is a fully packed and 10bits variant of NV12.
A luma pixel would take 10bits in memory, without any
filled bits between pixels in a stride. The color gamut
follows the BT.2020 standard
This pixel format is a fully packed and 10bits variant of NV12.
A luma pixel would take 10bits in memory, without any
filled bits between pixels in a stride. The color gamut
follows the BT.2020 standard.
Signed-off-by: Randy Li
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm
The rockchip use fully packed pixel format variants
for YUV 10bits.
This patch only make the VOP accept this pixel format,
but it doesn't add the converting data path for
the color gamuts that the target display are supported.
Signed-off-by: Randy Li
---
drivers/gpu/drm/roc
need to
set the plane offset and stride when you are using the other files.
Randy Li (2):
drm/fourcc: add a 10bits fully packed variant of NV12
drm/rockchip: Support 10 bits yuv format in vop
drivers/gpu/drm/drm_fourcc.c| 1 +
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 27
On 01/22/2018 12:09 PM, JeffyChen wrote:
Hi Randy,
On 01/22/2018 10:15 AM, JeffyChen wrote:
Hi Randy,
On 01/22/2018 09:18 AM, Randy Li wrote:
Also the power domain driver could manage the clocks as well, I would
suggest to use pm_runtime_*.
actually the clocks required by pm domain may
cks as well, I would
suggest to use pm_runtime_*.
Robin.
___
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linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
Randy Li
32
mask);
+void rga_start(struct rockchip_rga *rga);
+void rga_cmd_set(struct rga_ctx *ctx, void *src_mmu_pages, void
*dst_mmu_pages);
+
+#endif
--
Randy Li
The only adc button connected to adc input is recovery button.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288-firefly-reload.dts | 17 +
arch/arm/boot/dts/rk3288-firefly.dtsi | 13 +
2 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288
.
Signed-off-by: Randy Li
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 68ba7d4..886b249 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip
On 05/09/2017 03:40 PM, Guillaume Tucker wrote:
On 09/05/17 02:16, Randy Li wrote:
On 05/09/2017 12:27 AM, Heiko Stübner wrote:
Am Mittwoch, 3. Mai 2017, 10:56:24 CEST schrieb Guillaume Tucker:
The ARM Mali Midgard GPU kernel driver is only available
out-of-tree and is not going to be
the whole series, including the binding doc, after the merge
window if nobody complains before that :-)
Heiko
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linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
Randy Li
this patch currently.
I am not sure whether it is necessary to add a new function
at generic power domain. I want someone give me some advises
here.
Signed-off-by: Caesar Wang
Signed-off-by: Jeffy Chen
Signed-off-by: Randy Li
---
drivers/soc/rockchip/pm_domains.c | 24 ++
sensor at the botton of the panel
is also enabled.
The Firefly RK3288 Reload use a different GPIO pin to enable
the power of the eDP panel.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 112 ++
1 file changed, 112 insertions(+)
diff --git a
The only adc button connected to adc input is recovery button.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288-firefly-reload.dts | 17 +
arch/arm/boot/dts/rk3288-firefly.dtsi | 13 +
2 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288
This patch adds the supporting to the eDP panel sold by
the T-CHIP for the Firefly RK3288.
The InvenSense MPU6050 sensor at the botton of the panel
is also enabled.
The Firefly RK3288 Reload use a different GPIO pin to enable
the power of the eDP panel.
Signed-off-by: Randy Li
---
arch/arm
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288-firefly.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dts
b/arch/arm/boot/dts/rk3288-firefly.dts
index 14271be..b3964c8 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dts
o the bootloader.
ARM: rockchip: rk3288: Switch to use the proper PWM IP
Randy Li (2):
ARM: dts: rockchip: add eDP panel support for Firefly
ARM: dts: rockchip: enable eDP panel at Firefly Release
arch/arm/boot/dts/rk3288-firefly.dts | 28 +++
arch/arm/boot/dts/rk3288-firefly.dtsi
: I4e8a34609d5b292d7da77385ff15bebbf258090c
Signed-off-by: Randy Li
Signed-off-by: Randy Li
---
.../display/rockchip/analogix_dp-rockchip.txt | 4 ++
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 52 ++
2 files changed, 56 insertions(+)
diff --git
a/Documentation
The PWM devices need to access the grf to switch the PWM IP.
And tsadc uses it to shutdown the system.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 26b8886
The rockchip use a special pixel format for those yuv pixel
format with 10 bits color depth.
Signed-off-by: Randy Li
---
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 1 +
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 34 ++---
drivers/gpu/drm/rockchip
the V4L2_PIX_FMT_P010,
which uses the unused 6 bits to store the next pixel. And with
the alignment requirement of the hardware, it usually would be
some extra space left at the end of a stride.
Signed-off-by: Randy Li
---
Documentation/media/uapi/v4l/pixfmt-p010.rst | 126
pixel format
V6: reversed Cb/Cr order in comments
v7: reversed Cb/Cr order in comments of header files, remove
the wrong part of commit message.
Cc: Daniel Stone
Cc: Ville Syrjälä
Signed-off-by: Randy Li
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm
kchip, although it is not common used pixel format,
but it could save lots of memory, it may be welcome by the
other vendor, also I think the 3GR serial from Intel would
use the same pixel format as the video IP comes from rockchip.
Randy Li (3):
drm_fourcc: Add new P010, P016 video format
v4l: Add
2017年01月17日 15:58, Randy Li wrote:
Hello:
I want to enable the video output at RK3288 Firefly board, but I
found if I enable CONFIG_DRM_FBDEV_EMULATION, the HDMI would crash
down sometimes but sometimes it works. After disable that opinion, I
never meet a problem. I have not verified it with eDP
] [] (do_work_pending) from []
(slow_work_pending+0xc/0x20)
[ 34.464856] ---[ end trace 95ed2c3f167607d5 ]---
--
Randy Li
The third produce department
===
This email message, including any attachments, is for the sole
use of the intended
s new decoder has supported those 10 bits format for
profile_10 HEVC/AVC video.
Signed-off-by: Randy Li
v4l2
---
Documentation/media/uapi/v4l/pixfmt-p010.rst | 86
Documentation/media/uapi/v4l/pixfmt-p010m.rst | 94 ++
Documentation/media/uapi/v4l/pixfmt-p016.rst
pixel formats in v4l2, as it doesn't have a flag like drm does.
I have not met the usage of those 16 bits per-channel format,
it is a very large color range, even the DSLR only use 12 bits.
Randy Li (2):
drm_fourcc: Add new P010, P016 video format
[media] v4l: Add 10/16-bits per channel YUV
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format. Rockchip's vop support this
video format(little endian only) as the input video format.
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits
per channel video format.
Signed-off-by: Randy Li
On 01/03/2017 09:02 AM, Caesar Wang wrote:
在 2017年01月03日 07:57, Randy Li 写道:
On 01/02/2017 09:16 PM, Caesar Wang wrote:
在 2016年12月31日 00:11, ayaka 写道:
BTW, Caesar have you ever met this at RK3288 at booting time?
[8.430582] thermal thermal_zone1: critical temperature
reached(125 C
On 01/02/2017 09:16 PM, Caesar Wang wrote:
在 2016年12月31日 00:11, ayaka 写道:
BTW, Caesar have you ever met this at RK3288 at booting time?
[8.430582] thermal thermal_zone1: critical temperature
reached(125 C),shutting down
[8.439038] thermal thermal_zone2: critical temperature
reached(
Those pixel formats comes from Gstreamer and ffmpeg. Currently,
the VOP(video output mixer) found on RK3288 and future support
those pixel formats are input. Also the decoder on RK3288
could use them as output.
Randy Li (2):
drm_fourcc: Add new P010 video format
[media] v4l: Add 10-bits per
C/AVC video.
Signed-off-by: Randy Li
---
include/uapi/linux/videodev2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 46e8a2e3..9e03f20 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videod
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format. Rockchip's vop support this
video format(little endian only) as the input video format.
Signed-off-by: Randy Li
---
include/uapi/drm/drm_fourcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/in
en my patch might be some wrong.. :(
Best Regards,
Jaehoon Chung
[snip]
--
Randy Li
The third produce department
===
This email message, including any attachments, is for the sole
use of the intended rec
On 12/29/2016 03:25 PM, Shawn Lin wrote:
On 2016/12/29 15:13, Jaehoon Chung wrote:
On 12/29/2016 12:02 PM, Jaehoon Chung wrote:
Hi Randy,
On 12/29/2016 12:34 AM, Randy Li wrote:
This reverts commit f90142683f04bcb0729bf0df67a5e29562b725b9.
It is reported that making RK3288 can't boot
This reverts commit f90142683f04bcb0729bf0df67a5e29562b725b9.
It is reported that making RK3288 can't boot from eMMC/MMC.
Signed-off-by: Randy Li
---
drivers/mmc/host/dw_mmc-rockchip.c | 41 +++---
1 file changed, 3 insertions(+), 38 deletions(-)
diff --
, add the missing doc in the last
commit.
v4
1. Adding the reset callback in struct phy_ops.
2. Moving the reset into phy rockchip usb.
3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
Rebased from previous commit
v2
Rebased from previous commit
v1
orignal from google
Randy Li (2
e bus get
wedged.
Signed-off-by: Randy Li
Acked-by: John Youn
---
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/core_intr.c | 11 +++
drivers/usb/dwc2/platform.c | 9 +
3 files changed, 21 insertions(+)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
inde
reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file cha
On 10/28/2016 05:11 PM, Shawn Lin wrote:
On 2016/10/23 3:18, Randy Li wrote:
I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first. The eDP_AVDD_1V8 more
likely to be
I forget to add a dummy function in case the CONFIG_GENERIC_PHY
is disabled.
Signed-off-by: Randy Li
---
include/linux/phy/phy.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ee1bed7..78bb0d7 100644
--- a/include/linux/phy
I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first. The eDP_AVDD_1V8 more
likely to be applied to eDP phy, but I have no time to confirmed
it yet.
Signed-off-by: Randy Li
e bus get
wedged.
Signed-off-by: Randy Li
---
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/core_intr.c | 11 +++
drivers/usb/dwc2/platform.c | 9 +
3 files changed, 21 insertions(+)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 2a21a04..e91ddbc
in the last
commit.
v4
1. Adding the reset callback in struct phy_ops.
2. Moving the reset into phy rockchip usb.
3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
Rebased from previous commit
v2
Rebased from previous commit
v1
orignal from google
Randy Li (2):
usb: dwc2
reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file cha
On 10/20/2016 03:18 PM, Tomeu Vizoso wrote:
On 19 October 2016 at 15:52, Randy Li wrote:
Hello,
Recently, I want to use a eDP panel in my RK3288 platform, but I got the
following message:
[8.935918] i2c i2c-6: of_i2c: modalias failure on /dp@ff97/ports
[8.936018] rockchip-drm
On 10/20/2016 06:58 AM, John Youn wrote:
On 10/15/2016 8:07 AM, 陈豪 wrote:
2016-09-25 2:50 GMT+08:00 Randy Li :
On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspen
Hello,
Recently, I want to use a eDP panel in my RK3288 platform, but I got
the following message:
[8.935918] i2c i2c-6: of_i2c: modalias failure on /dp@ff97/ports
[8.936018] rockchip-drm display-subsystem: bound ff97.dp (ops
rockchip_dp_component_ops [analogix_dp_rockchip])
WM8960 analog audio codec is also
enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace converter.
Signed-off-by: Randy Li
Reviewed-by: Krzysztof Kozlowski
---
.../bindings/arm/samsung/samsung-boards.txt| 3 +
arch/arm/boot/dts/Makefile
- v2:
- removing rtc node
the clock source driver is not done yet.
- adding exynos-bus
- fixing the MFC
Randy Li (2):
ARM: dts: Add TOPEET itop core board SCP package version
ARM: dts: add TOPEET itop elite based board
.../bindings/arm/samsung/samsung-boards.txt| 3 +
arch/arm
-by: Randy Li
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501
1 file changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
b/arch/arm/boot/dts/exynos4412-itop
, and it is a little hard to debug as
kernel still would never kill that task.
Randy Li
--
Randy Li
The third produce department
===
This email message, including
From: Randy Li
Organization: Fuzhou Rockchip
To: david...@rock-chips.com
CC: roger.c...@rock-chips.com
Hello Wu
Have you guys confirmed the RK3288 EVB with 1000Mbps network? I meet
this issue in the weekend. The kernel is 4.4, when I connected the board
into a 1000Mbps switch(Dell PowerConnect S
I forget to add a dummy function in case the CONFIG_GENERIC_PHY
is disabled.
Signed-off-by: Randy Li
---
include/linux/phy/phy.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ee1bed7..78bb0d7 100644
--- a/include/linux/phy
reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file cha
e bus get
wedged.
Signed-off-by: Randy Li
---
drivers/usb/dwc2/core_intr.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..af27edc 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/cor
based from previous commit
v2
Rebased from previous commit
v1
orignal from google
Randy Li (3):
phy: Add reset callback for not generic phy
usb: dwc2: assert phy reset when waking up in rk3288 platform
ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset
arch/arm/boot/dts/r
The timings issue is still here, this version is just some modifications
in dts file.
Randy Li (2):
ARM: dts: samsung: add rga-lvds panel in itop elite
drm/panel: Add support for Chunghwa CLAA070WP03XG panel
.../display/panel/chunghwa,claa070wp03xg.txt | 7 +++
arch/arm/boot/dts
It is actually a lvds panel connected through a rga-lvds bridge.
The touchscreen is communicated with i2c bus but the driver is not
support now.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/exynos4412-itop-elite.dts | 54 +++--
1 file changed, 52 insertions(+), 2
The Chunghwa CLAA070WP03XG is a 7" 1280x800 panel, which can be
supported by the simple panel driver.
Signed-off-by: Randy Li
---
.../display/panel/chunghwa,claa070wp03xg.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 27 ++
2 files change
y new board
would need them.
Signed-off-by: Randy Li
---
sound/soc/samsung/Kconfig | 57 ---
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 7b722b0..f6023b4 100644
--- a/soun
It is simple sound card time, we could assign different codec
to a interface without making a specific driver for it. The SPDIF
and I2S interface for Samsung would be possible used by simple-sound-card,
but not sure about the PCM.
Signed-off-by: Randy Li
---
sound/soc/samsung/Kconfig | 16
-by: Randy Li
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501
1 file changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
b/arch/arm/boot/dts/exynos4412-itop
WM8960 analog audio codec is also
enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace convertor.
Signed-off-by: Randy Li
Reviewed-by: Krzysztof Kozlowski
---
.../bindings/arm/samsung/samsung-boards.txt| 3 +
arch/arm/boot/dts/Makefile
dding exynos-bus
- fixing the MFC
Randy Li (2):
ARM: dts: Add TOPEET itop core board SCP package version
ARM: dts: add TOPEET itop elite based board
.../bindings/arm/samsung/samsung-boards.txt| 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exyno
.inv_vsync = 0,
.inv_vden = 0,
},
}
Randy Li (2):
ARM: dt
The Chunghwa CLAA070WP03XG is a 7" 1280x800 panel, which can be
supported by the simple panel driver.
Signed-off-by: Randy Li
---
.../display/panel/chunghwa,claa070wp03xg.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 27 ++
2 files change
It is actually a lvds panel connected through a rga-lvds bridge.
The touchscreen is communicated with i2c bus but the driver is not
support now.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/exynos4412-itop-elite.dts | 54 +++--
1 file changed, 52 insertions(+), 2
It is simple sound card time, we could assign different codec
to a interface without making a specific driver for it.
Signed-off-by: Randy Li
---
sound/soc/samsung/Kconfig | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung
I found those modules should be selected directly, as I
only use the simple sound card.
Randy Li (1):
ASoC: samsung: make audio interface/controller explicitly
sound/soc/samsung/Kconfig | 8
1 file changed, 4 insertions(+), 4 deletions(-)
--
2.7.4
-by: Randy Li
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 491
1 file changed, 491 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
b/arch/arm/boot/dts/exynos4412-itop
Add TOPEET, a ARM devlopment board vendor in China mainland.
Signed-off-by: Randy Li
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation
- v2:
- removing rtc node
the clock source driver is not done yet.
- adding exynos-bus
- fixing the MFC
Randy Li (3):
ARM: dts: Add TOPEET itop core board SCP package version
ARM: dts: add TOPEET itop elite based board
devicetree: bindings: Add vendor prefix for Topeet.
.../bindings/arm/sa
WM8960 analog audio codec is also
enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace convertor.
Signed-off-by: Randy Li
---
.../bindings/arm/samsung/samsung-boards.txt| 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts
reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Signed-off-by: Randy Li
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file cha
lite board
- suuport the audio codec at elite board
- fixing minor bugs in the last commit
- v2:
- removing rtc node
the clock source driver is not done yet.
- adding exynos-bus
- fixing the MFC
Randy Li (4):
phy: Add reset callback
phy: rockchip-usb: use rockchip_usb_phy_reset to
It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.
Signed-off-by: Randy Li
---
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 3 +++
drivers/phy/phy-rockchip-usb.c | 20
2 files changed, 23 insertions(+)
diff --git
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