On Tue, Apr 13, 2021 at 11:51 AM Marc Zyngier wrote:
>
> On Tue, 13 Apr 2021 16:03:51 +0100,
> Peter Geis wrote:
> >
> > On Tue, Apr 13, 2021 at 10:01 AM Marc Zyngier wrote:
>
> [...]
>
> > > What happens if you hack all the allocations to happen in the lo
On Tue, Apr 13, 2021 at 10:01 AM Marc Zyngier wrote:
>
> On Tue, 13 Apr 2021 14:29:32 +0100,
> Peter Geis wrote:
> >
> > On Tue, Apr 13, 2021 at 5:23 AM Marc Zyngier wrote:
> > >
> > > Hi Peter,
> > >
> > > On Mon, 12 Apr 2021 21:4
On Mon, Apr 12, 2021 at 6:38 PM Johan Jonker wrote:
>
> Currently all gpio nodenames are sort of identical to there label.
> Nodenames should be of a generic type, so change them all.
Currently the rockchip pinctrl driver checks np->name against the
bank->name and if they do not match it does not
ce you can provide would be greatly appreciated.
Very Respectfully,
Peter Geis
On Mon, Apr 12, 2021 at 9:34 AM Andy Shevchenko
wrote:
>
> On Mon, Apr 12, 2021 at 4:30 PM Heiko Stübner wrote:
> > Am Montag, 12. April 2021, 14:13:37 CEST schrieb Andy Shevchenko:
> > > On Sun, Apr 11, 2021 at 4:35 PM Peter Geis wrote:
> > > >
> > >
From: Jianqun Xu
The next version gpio controller on SoCs like rk3568 have more write
mask bits for registers.
Signed-off-by: Jianqun Xu
---
drivers/gpio/gpio-rockchip.c | 280 ++---
drivers/pinctrl/pinctrl-rockchip.h | 2 +
2 files changed, 215 insertions(+), 6
From: Jianqun Xu
Store register offsets in the struct rockchip_gpio_regs, this patch
prepare for the driver update for new gpio controller.
Signed-off-by: Jianqun Xu
---
drivers/gpio/gpio-rockchip.c | 85 --
drivers/pinctrl/pinctrl-rockchip.h | 38
From: Jianqun Xu
There has spin lock for irq set type already, so drop irq_gc_lock and
irq_gc_unlock.
Signed-off-by: Jianqun Xu
---
drivers/gpio/gpio-rockchip.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 048e7eecddba..
From: Jianqun Xu
Since gate and ungate pclk of gpio has very litte benifit for system
power consumption, just keep it always ungate.
Signed-off-by: Jianqun Xu
---
drivers/gpio/gpio-rockchip.c | 68 +---
1 file changed, 9 insertions(+), 59 deletions(-)
diff --gi
From: Jianqun Xu
Store a pointer from the pinctrl device for the gpio bank.
Signed-off-by: Jianqun Xu
---
drivers/pinctrl/pinctrl-rockchip.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.h
b/drivers/pinctrl/pinctrl-rockchip.h
index dba9e9540633..4aa3d2
From: Jianqun Xu
Separate the gpio driver from the pinctrl driver.
Signed-off-by: Jianqun Xu
---
drivers/gpio/Kconfig | 8 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-rockchip.c | 657 +++
drivers/pinctrl/pinctrl-rockchip.c | 68
From: Jianqun Xu
Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will
be used by gpio-rockchip driver in the future.
Signed-off-by: Jianqun Xu
---
drivers/pinctrl/pinctrl-rockchip.c | 226 +-
drivers/pinctrl/pinctrl-rockchip.h | 245 +
Separate gpio driver from pinctrl driver, and support v2 controller.
Tested on rk3566-quartz64 prototype board.
Patch History:
V2 - Rebase to latest linux-next.
Tested-by: Peter Geis
Jianqun Xu (7):
pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
pinctrl/pinctrl
On Sat, Feb 20, 2021 at 12:36 PM Matthew Wilcox wrote:
>
> On Sat, Feb 20, 2021 at 12:29:18PM -0500, Peter Geis wrote:
> > Good Afternoon,
> >
> > I have been tracking down a regular bug that triggers when running OpenWRT
> > in a lxd container.
> > Ever
803.240024] 1015296 pages RAM
[2121803.240027] 0 pages HighMem/MovableOnly
[2121803.240030] 42695 pages reserved
[2121803.240032] 8192 pages cma reserved
[2121803.240035] 0 pages hwpoisoned
Thank you for your time.
Very Respectfully,
Peter Geis
-Added ack and reviewed-by from Jon
-Updated fix to apply to tegra30-hda vice universally (Thanks Jon)
-Updated commit to include comments from hardware team (Thanks Sameer)
-Cleaned up commit messages
Peter Geis (2):
clk: tegra30: Add hda clock default rates to clock driver
ALSA: hda/tegra: fix
: Peter Geis
---
drivers/clk/tegra/clk-tegra30.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 37244a7e68c2..9cf249c344d9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1256,6
issue on tegra30-hda.
Tested on the Ouya game console and the tf201 tablet.
[1] commit 60019d8c650d ("ALSA: hda/tegra: workaround playback failure on
Tegra194")
Reviewed-by: Jon Hunter
Tested-by: Ion Agorria
Signed-off-by: Peter Geis
---
sound/pci/hda/hda_tegra.c | 2 +-
1 file chan
On Fri, Jan 8, 2021 at 6:33 AM Jon Hunter wrote:
>
>
> On 08/01/2021 10:54, Jon Hunter wrote:
> >
> > On 08/01/2021 08:00, Sameer Pujar wrote:
> >
> > ...
> >
> >>>>> Signed-off-by: Peter Geis
> >>>>> Tested-by: Ion Ago
. It is unknown why this
occurs, though it is likely related to other eMMC limitations experienced
on Ouya.
For now, fix it by enabling input on cam_mclk_pcc0.
Fixes: d7195ac5c9c5 ("ARM: tegra: Add device-tree for Ouya")
Reported-by: Matt Merhar
Tested-by: Matt Merhar
Signed-off-by:
d-by: Matt Merhar
Signed-off-by: Peter Geis
---
Changes v2:
-Added stable tag.
-Improved commit message.
arch/arm/boot/dts/tegra30-ouya.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts
b/arch/arm/boot/dts/tegra30-ouya.dts
index 74
On Tue, Jan 5, 2021 at 1:30 AM Sameer Pujar wrote:
>
>
>
> On 12/25/2020 6:50 AM, Peter Geis wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > Currently hda on tegra30 fails to open a stream with an input/output error.
> >
sdmmc4 in the primary pin configuration so it is unknown why this
occurs.
It is likely related to the other emmc limitations we have on Ouya.
For now, fix it by enabling input on cam_mclk_pcc0.
Fixes: d7195ac5c9c5 ("ARM: tegra: Add device-tree for Ouya")
Signed-off-by: Peter Geis
R
manifested.
Applying the fix in [1] universally resolves this issue on tegra30.
Tested on the Ouya game console and the tf201 tablet.
[1] 60019d8c650d ("ALSA: hda/tegra: workaround playback failure on Tegra194")
Signed-off-by: Peter Geis
Tested-by: Ion Agorria
---
sound/pci/hda/hda_teg
Current implementation defaults the hda clocks to clk_m.
This causes hda to run too slow to operate correctly.
Fix this by defaulting to pll_p and setting the frequency to the correct rate.
This matches upstream t124 and downstream t30.
Signed-off-by: Peter Geis
Tested-by: Ion Agorria
that downstream devices used the spdif device instead of hda for hdmi
audio.
The spdif device lacks a driver on mainline.
Peter Geis (2):
clk: tegra30: Add hda clock default rates to clock driver
ALSA: hda/tegra: fix tegra-hda on tegra30 soc
drivers/clk/tegra/clk-tegra30.c | 2 ++
sound/pci
On Wed, Oct 7, 2020 at 12:08 PM Stephen Warren wrote:
>
>
> This definitely isn't the correct attitude to copyright.
>
> The facts[1] that Ouya published the code and that it used GPL-only
> symbols certainly does imply that they *should* have published under GPL
> or a compatible license, but doe
On Mon, Oct 5, 2020 at 6:29 PM Alexandre Belloni
wrote:
>
> On 05/10/2020 09:13:08-0400, Peter Geis wrote:
> > Good Morning,
> >
> > While testing suspend to ram on the Ouya, I encountered an interesting
> > issue with the rtc-tps65910 driver.
> > Attem
On Mon, Oct 5, 2020 at 10:02 AM Dmitry Osipenko wrote:
>
> 04.10.2020 16:31, Peter Geis пишет:
> > + thermal-zones {
> > + cpu_thermal: cpu-thermal {
> > + polling-delay = <5000>;
> > +
your time.
Very Respectfully,
Peter Geis
Ouya is a defunct company from 2012 to 2015.
They produced a single device, the Ouya game console.
In 2015 they were purchased by Razer Inc. and the Ouya was discontinued.
All Ouya services were shuttered in 2019.
Signed-off-by: Peter Geis
Acked-by: Rob Herring
---
Documentation/devicetree
Add a binding for the Tegra30-based Ouya game console.
Signed-off-by: Peter Geis
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml
b/Documentation/devicetree
per Dmitry Osipenko's review.
- Enable lp1 sleep mode.
- Fix bluetooth comment and add missing power supplies.
v2: - Update pmic and clock handles per Rob Herring's review.
- Add acks from Rob Herring to patch 2 and 3.
Peter Geis (3):
ARM: tegra: Add device-tree for Ouy
On Tue, Sep 15, 2020 at 1:00 PM Randy Dunlap wrote:
>
> On 9/15/20 4:41 AM, Peter Geis wrote:
> > [33633.566567] [] (unwind_backtrace) from []
> > (show_stack+0x10/0x14)
>
> Hi Peter,
>
> In the future, could you prevent long lines from being line-wrapped?
> E.g.
On Thu, Sep 24, 2020 at 8:12 PM Dmitry Osipenko wrote:
>
> ...
> > +/ {
> > + model = "Ouya Game Console";
> > + compatible = "ouya,ouya", "nvidia,tegra30";
> > +
> > + aliases {
> > + rtc0 = &pmic;
> > + rtc1 = "/rtc@7000e000";
> > + serial0 = &uart
Good Day,
This series introduces upstream kernel support for the Ouya game console
device. Please review and apply. Thank you in advance.
Changelog:
v2: - Update pmic and clock handles per Rob Herring's review.
- Add acks from Rob Herring to patch 2 and 3.
Peter Geis (3):
ARM:
Ouya is a defunct company from 2012 to 2015.
They produced a single device, the Ouya game console.
In 2015 they were purchased by Razer Inc. and the Ouya was discontinued.
All Ouya services were shuttered in 2019.
Signed-off-by: Peter Geis
Acked-by: Rob Herring
---
Documentation/devicetree
Add a binding for the Tegra30-based Ouya game console.
Signed-off-by: Peter Geis
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml
b/Documentation/devicetree
Ouya is a defunct company from 2012 to 2015.
They produced a single device, the Ouya game console.
In 2015 they were purchased by Razer Inc. and the Ouya was discontinued.
All Ouya services were shuttered in 2019.
Signed-off-by: Peter Geis
---
Documentation/devicetree/bindings/vendor
Good Day,
This series introduces upstream kernel support for the Ouya game console
device. Please review and apply. Thank you in advance.
Peter Geis (3):
ARM: tegra: Add device-tree for Ouya
dt-bindings: Add vendor prefix for Ouya Inc.
dt-bindings: ARM: tegra: Add Ouya game console
Add a binding for the Tegra30-based Ouya game console.
Signed-off-by: Peter Geis
---
Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml
b/Documentation/devicetree/bindings/arm/tegra.yaml
index
On Wed, Sep 16, 2020 at 10:17 AM Dmitry Osipenko wrote:
>
> 16.09.2020 15:22, Peter Geis пишет:
> > The Ouya was the sole device produced by Ouya Inc in 2013.
> > It was a game console originally running Android 5 on top of Linux 3.1.10.
> >
> > This patch adds the d
Good Morning,
I discovered a double free bug in kmalloc-128 in v5.9 on arm.
It is with the tegra_defconfig, running on a tegra30.
I've reliably reproduced it by compiling the kernel on the board then rebooting.
It will sometimes trigger early into compilation.
I've begun bisecting and will report
On Thu, Aug 6, 2020 at 6:22 PM Russell King - ARM Linux admin
wrote:
>
> On Thu, Aug 06, 2020 at 05:46:50PM -0400, Peter Geis wrote:
> > Good Evening,
> >
> > I had attempted to get this working as well, but have run into
> > difficulties with both my implementa
mall");
+ break;
case ZSTD_error_corruption_detected:
- case ZSTD_error_checksum_wrong:
error("ZSTD-compressed data is corrupt");
break;
+ case ZSTD_error_checksum_wrong:
+ error("ZSTD-compressed data checksum is wrong");
+ break;
default:
error("ZSTD-compressed data is probably corrupt");
break;
Very Respectfully,
Peter Geis
On Thu, Jun 11, 2020 at 9:06 PM Peter Geis wrote:
>
> Good Evening,
>
> I am currently testing this on the rk3399-rockpro64, and it appears to
> fully fix the gmac problem without using txpbl.
> PCIe also seems to be more stable at high load.
> I need to conduct long term tes
k3328 gmac controller.
Tested-by: Peter Geis
On Mon, Jun 8, 2020 at 9:15 PM Sugar Zhang wrote:
>
>
>
> Changes in v2:
> - fix FATAL ERROR: Unable to parse input tree
>
> Sugar Zhang (13):
> dmaengine: pl330: Remove the burst limit for quirk 'NO-FLUSHP'
> dma
On Wed, Oct 16, 2019 at 9:29 AM Dmitry Osipenko wrote:
>
> 16.10.2019 08:18, Viresh Kumar пишет:
> > On 16-10-19, 00:16, Dmitry Osipenko wrote:
> >> Re-parenting to intermediate clock is supported now by the clock driver
> >> and thus there is no need in a customized CPUFreq driver, all that code
Tested on the Ouya (tegra30).
Tested-by: Peter Geis
On Wed, Oct 2, 2019 at 9:56 AM Dmitry Osipenko wrote:
>
> 02.10.2019 03:25, Chanwoo Choi пишет:
> > Hello Dmitry and Thierry,
> >
> > On 19. 10. 2. 오전 6:15, Dmitry Osipenko wrote:
> >> 12.08.2019 00:22, D
Tested on the Ouya (tegra30).
Tested-by: Peter Geis
On Sun, Aug 11, 2019 at 5:02 PM Dmitry Osipenko wrote:
>
> Introduce driver for the External Memory Controller (EMC) found on Tegra30
> chips, it controls the external DRAM on the board. The purpose of this
> driver is to pr
The Ouya (tegra30) hard locks when the emc clock drops below 400mhz.
Discovered while testing the devfreq and emc drivers.
This patch resolves that issue.
Tested-by: Peter Geis
On Tue, Jul 30, 2019 at 2:10 PM Dmitry Osipenko wrote:
>
> Turned out that WFI doesn't work reliably on T
- aclk_h264
- hclk_h264
- aclk_axisram
- aclk_gmac
- aclk_usb3otg
Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Signed-off-by: Jonas Karlman
Tested on the rk3328-roc-cc.
Tested-by: Peter Geis
---
drivers/clk/rockchip/clk-rk3328.c | 18 +-
1 file
On 08/09/2018 08:37 AM, Aapo Vienamo wrote:
On Thu, 9 Aug 2018 08:23:16 -0400
Peter Geis wrote:
On 08/09/2018 08:02 AM, Aapo Vienamo wrote:
On Thu, 9 Aug 2018 13:49:22 +0200
Thierry Reding wrote:
On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote:
Add the HS400 DQS trim
On 08/09/2018 08:02 AM, Aapo Vienamo wrote:
On Thu, 9 Aug 2018 13:49:22 +0200
Thierry Reding wrote:
On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote:
Add the HS400 DQS trim value for Tegra186 SDMMC4.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi |
On 7/28/2018 6:13 AM, Dmitry Osipenko wrote:
On Friday, 27 July 2018 23:19:53 MSK Peter Geis wrote:
Kingston KE4CN3K6A.
Though I am pretty sure I've figured out the instability.
Brought it in to work and hooked it to a scope.
Couldn't find clock, but cmd and all eight bits are runn
ticed that even on the slowest slew rate there is significant
ringing and overshoot of .15 volts.
On Fri, Jul 27, 2018, 15:52 Dmitry Osipenko wrote:
> On Thursday, 26 July 2018 20:48:55 MSK Peter Geis wrote:
> > On 07/26/2018 01:36 PM, Stefan Agner wrote:
> > > On 26.07.
On 07/26/2018 01:36 PM, Stefan Agner wrote:
On 26.07.2018 18:39, Peter Geis wrote:
I finally got around to testing this on the Ouya (Tegra 3).
Thanks for testing!
I found that the "Got command interrupt 0x0001 even though no
command operation was in progress." error occ
I finally got around to testing this on the Ouya (Tegra 3).
Thanks for testing!
I found that the "Got command interrupt 0x0001 even though no
command operation was in progress." error occurred when the interface
is unstable.
I've had a lot of problems with sdmmc4 stability on the Ouya abo
On 07/26/2018 10:47 AM, Stefan Agner wrote:
On 26.07.2018 15:56, Peter Geis wrote:
On 07/12/2018 03:39 AM, Stefan Agner wrote:
It seems that SD3.0 advertisement needs to be set for higher eMMC
speed modes (namely DDR52) as well. The TRM states that the SD3.0
advertisement bit should be set for
On 07/12/2018 03:39 AM, Stefan Agner wrote:
It seems that SD3.0 advertisement needs to be set for higher eMMC
speed modes (namely DDR52) as well. The TRM states that the SD3.0
advertisement bit should be set for all controller instances, even
for those not supporting UHS-I mode...
When specifyin
On 7/25/2018 7:24 PM, Stephen Boyd wrote:
Quoting Marcel Ziswiler (2018-07-20 00:54:22)
From: Marcel Ziswiler
Actually report the error code from devm_regulator_get() which may as
well just be a probe deferral.
Signed-off-by: Marcel Ziswiler
---
drivers/clk/tegra/clk-dfll.c | 5 +++--
1
On 07/24/2018 10:29 AM, Aapo Vienamo wrote:
Aapo Vienamo (10):
mmc: tegra: Enable pad calibration on Tegra210 and Tegra186
Good Morning,
You seem to be missing patch 10/10.
Checked
https://lore.kernel.org/patchwork/project/lkml/list/?series=360525 to be
sure.
On 07/24/2018 10:36 AM, Mark Brown wrote:
On Tue, Jul 24, 2018 at 09:25:40AM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on
On 07/24/2018 10:48 AM, Dmitry Osipenko wrote:
On Tuesday, 24 July 2018 17:45:01 MSK Marcel Ziswiler wrote:
On Tue, 2018-07-24 at 17:31 +0300, Dmitry Osipenko wrote:
On Tuesday, 24 July 2018 17:16:33 MSK Marcel Ziswiler wrote:
On Tue, 2018-07-24 at 15:44 +0300, Dmitry Osipenko wrote:
On T
Added support for the CPCAP power management regulator functions on
Tegra based Motorola Xoom devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Xoom init tables and device tree compatibility match.
Signed-off-by: Peter Geis
---
.../bindings
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap-regulator.c | 23 +++
1
r for-next branch.
v1:
Fix conversion of tabulation to spaces.
Peter Geis (2):
Add sw2_sw4 voltage table to cpcap regulator.
Add support for CPCAP regulators on Motorola Xoom devices.
.../bindings/regulator/cpcap-regulator.txt| 1 +
drivers/regulator/cpcap-regulator.c
On 07/23/2018 08:27 PM, Dmitry Osipenko wrote:
On Monday, 23 July 2018 22:38:48 MSK Peter Geis wrote:
Added support for the CPCAP power management regulator functions on
Tegra devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Tegra init
On 07/23/2018 03:20 PM, Dmitry Osipenko wrote:
On Monday, 23 July 2018 21:37:50 MSK Peter Geis wrote:
On 07/23/2018 02:13 PM, Mark Brown wrote:
On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra
Added support for the CPCAP power management regulator functions on
Tegra devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Tegra init tables and device tree compatibility match.
Signed-off-by: Peter Geis
---
.../bindings/regulator/cpcap
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap-regulator.c | 23 +++
1
power the Tegra core, and a DT match
for the Tegra device.
Tested on the Motorola Xoom MZ602.
v2:
Stopped reinventing the wheel, using git email now.
Rebased against regulator for-next branch.
v1:
Fix conversion of tabulation to spaces.
Peter Geis (2):
Add sw2_sw4 voltage table to cpcap
On 07/23/2018 02:13 PM, Mark Brown wrote:
On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap-regulator.c | 23
Added support for the CPCAP power management regulator functions on
Tegra devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Tegra init tables and device tree compatibility match.
Signed-off-by: Peter Geis
---
.../bindings/regulator/cpcap
DT match for the Tegra device.
Tested on the Motorola Xoom MZ602.
v1:
Fix conversion of tabulation to spaces.
Peter Geis (2):
Add sw2_sw4 voltage table to cpcap regulator.
Add support for CPCAP regulators on Tegra devices.
.../bindings/regulator/cpcap-regulator.txt| 1 +
drivers
On 07/23/2018 01:01 PM, Mark Brown wrote:
On Fri, Jul 20, 2018 at 08:43:49PM -0400, Peter Geis wrote:
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on
Re-sending due to email address typo.
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap
Added support for the CPCAP power management regulator functions on
Tegra devices.
Added sw2_sw4 value tables, which provide power to the Tegra core and
aux devices.
Added the Tegra init tables and device tree compatibility match.
Signed-off-by: Peter Geis
---
.../bindings/regulator/cpcap
SW2 and SW4 use a shared table to provide voltage to the cpu core and
devices on Tegra hardware.
Added this table to the cpcap regulator driver as the first step to
supporting this device on Tegra.
Signed-off-by: Peter Geis
---
drivers/regulator/cpcap-regulator.c | 23
Good Evening,
The CPCAP regulator driver can support various devices, but currently
only supports Omap4 devices.
Adds the sw2 and sw4 voltage tables, which power the Tegra core, and a
DT match for the Tegra device.
Tested on the Motorola Xoom MZ602.
Peter Geis (2):
Add sw2_sw4 voltage
);
^~
Very Respectfully,
Peter Geis
On 07/03/2018 07:35 AM, Aapo Vienamo wrote:
From: Peter De Schrijver
Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.
Signed-off-by: Peter De-Schrijver
Signed-off-by: Aapo Vienamo
---
drivers/clk/tegra/Makefile
On 07/02/2018 10:48 AM, Dmitry Osipenko wrote:
On Friday, 29 June 2018 22:37:02 MSK Peter Geis wrote:
Good Afternoon,
I have tested these patches on the Ouya T3 device.
They work great to enable the L2 cache controller, however they do not
respect explicitly disabling the L2 cache
CONFIG_TRUSTED_FOUNDATIONS enabled,
the L2 cache controller is silently enabled and allows all four cores to
boot.
One must also disable CONFIG_TRUSTED_FOUNDATIONS to stop the L2 cache
controller from spinning up.
Tested-by: Peter Geis
On 06/19/2018 07:00 AM, Dmitry Osipenko wrote:
Hello,
This series of patches
On 06/05/2018 05:28 AM, Thierry Reding wrote:
On Mon, Jun 04, 2018 at 06:35:40PM +0300, Aapo Vienamo wrote:
The sdhci get_max_clock callback is set to sdhci_pltfm_clk_get_max_clock
and tegra_sdhci_get_max_clock is removed. It appears that the
shdci-tegra specific callback was originally intro
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