On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series does the following:
>
> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
> into common drivers/cpuidle/ directory.
>
> 2. Enables CPU cluster power-down idling state on Tegra
On Mon, Aug 05, 2019 at 02:03:29PM +0300, Dmitry Osipenko wrote:
> 05.08.2019 11:33, Peter De Schrijver пишет:
> > On Fri, Aug 02, 2019 at 05:39:23PM +0300, Dmitry Osipenko wrote:
> >> 02.08.2019 17:05, Peter De Schrijver пишет:
> >>> On Thu, Jul 25, 2019 at 06:18:32P
On Fri, Aug 02, 2019 at 05:39:23PM +0300, Dmitry Osipenko wrote:
> 02.08.2019 17:05, Peter De Schrijver пишет:
> > On Thu, Jul 25, 2019 at 06:18:32PM +0300, Dmitry Osipenko wrote:
> >> Add regulators coupler for Tegra30 SoCs that performs voltage balancing
> >> of a
On Thu, Jul 25, 2019 at 06:18:32PM +0300, Dmitry Osipenko wrote:
> Add regulators coupler for Tegra30 SoCs that performs voltage balancing
> of a coupled regulators and thus provides voltage scaling functionality.
>
> There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
> coupled
On Tue, Jul 30, 2019 at 08:40:19PM +0300, Dmitry Osipenko wrote:
> The PCLK clock is running off SCLK, which is a critical clock that is
> very unlikely to randomly change its rate. It is possible to get a
> lockup if kernel decides to enter LP2 cpuidle from a clk-notifier, which
> happens occasion
On Thu, Jul 25, 2019 at 01:59:09PM +0300, Dmitry Osipenko wrote:
> 25.07.2019 13:38, Peter De Schrijver пишет:
> > On Thu, Jul 25, 2019 at 01:33:48PM +0300, Peter De Schrijver wrote:
> >> On Thu, Jul 25, 2019 at 01:05:13PM +0300, Dmitry Osipenko wrote:
> >>> 25.07.
On Thu, Jul 25, 2019 at 01:33:48PM +0300, Peter De Schrijver wrote:
> On Thu, Jul 25, 2019 at 01:05:13PM +0300, Dmitry Osipenko wrote:
> > 25.07.2019 12:55, Peter De Schrijver пишет:
> > > On Mon, Jul 22, 2019 at 12:54:51PM +0300, Dmitry Osipenko wrote:
> > >>
>
On Thu, Jul 25, 2019 at 01:05:13PM +0300, Dmitry Osipenko wrote:
> 25.07.2019 12:55, Peter De Schrijver пишет:
> > On Mon, Jul 22, 2019 at 12:54:51PM +0300, Dmitry Osipenko wrote:
> >>
> >> All Tegra SoCs support SC7, hence the 'supports_sc7' and the com
On Mon, Jul 22, 2019 at 12:54:51PM +0300, Dmitry Osipenko wrote:
>
> All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
> doesn't sound correct to me. Something like 'firmware_sc7' should suit
> better here.
>
> > + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CL
On Thu, Jul 18, 2019 at 10:45:31AM +0100, Jon Hunter wrote:
>
> On 08/07/2019 00:08, Dmitry Osipenko wrote:
> > The PCLK clock is running off SCLK, which is a critical clock that is
> > very unlikely to randomly change its rate. It's also a bit clumsy (and
> > apparently incorrect) to query the cl
a/reset-handler.S | 6 +++---
> > arch/arm/mach-tegra/sleep-tegra30.S | 4 +++-
> > drivers/soc/tegra/flowctrl.c| 19 +--
> > 3 files changed, 23 insertions(+), 6 deletions(-)
> >
>
> Hello Peter,
>
> We were talking about these fixes on the IRC not so long time ago, does
> it look good to you? Care to give an ACK?
Acked-By Peter De Schrijver
On Tue, Jul 23, 2019 at 05:35:10AM +0300, Dmitry Osipenko wrote:
> The PCLK clock is running off SCLK, which is a critical clock that is
> very unlikely to randomly change its rate. It's also a bit clumsy (and
> apparently incorrect) to query the clock's rate with interrupts being
> disabled becaus
On Thu, Jul 18, 2019 at 02:44:56AM +0300, Dmitry Osipenko wrote:
> >
> > dependencies I am referring are dfll_ref, dfll_soc, and DVFS peripheral
> > clocks which need to be restored prior to DFLL reinit.
>
> Okay, but that shouldn't be a problem if clock dependencies are set up
> properly.
>
> >
On Tue, Jul 16, 2019 at 09:43:16PM +0300, Dmitry Osipenko wrote:
> > CPU parents are PLL_X, PLL_P, and dfll. PLL_X always runs at higher rate
> > so switching to PLL_P during CPUFreq probe prior to dfll clock enable
> > should be safe.
>
> AFAIK, PLLX could run at ~200MHz. There is also a divided
On Tue, Jul 16, 2019 at 09:25:43PM +0300, Dmitry Osipenko wrote:
> 16.07.2019 21:19, Sowjanya Komatineni пишет:
> >
> > On 7/16/19 9:50 AM, Sowjanya Komatineni wrote:
> >>
> >> On 7/16/19 8:00 AM, Dmitry Osipenko wrote:
> >>> 16.07.2019 11:06, Peter De
On Tue, Jul 16, 2019 at 03:24:26PM +0800, Joseph Lo wrote:
> > OK, Will add to CPUFreq driver...
> > >
> > > The other thing that also need attention is that T124 CPUFreq driver
> > > implicitly relies on DFLL driver to be probed first, which is icky.
> > >
> > Should I add check for successful d
external memory on
> the EMC clock rate change. The driver was tested using the ACTMON devfreq
> driver that performs memory frequency scaling based on memory-usage load.
Acked-By: Peter De Schrijver
On Fri, May 24, 2019 at 08:23:46PM +0300, Dmitry Osipenko wrote:
> A proper External Memory Controller clock rounding and parent selection
> functionality is required by the EMC drivers. It is not available using
> the generic clock implementation, hence add a custom one. The clock rate
> rounding
On Tue, May 28, 2019 at 04:08:44PM -0700, Sowjanya Komatineni wrote:
> This patch series includes Tegra210 deepsleep/LP0 support with
> deep sleep exit through RTC alarm wake and power button wake events.
>
We have been calling this SC7 (system C-state 7) for quite a while now.
Peter.
> Note: W
where
> appropriate, the newer Tegra210 is getting support for microsecond
> clocksource and the driver's code is getting much cleaner.
>
> The series was extensively tested on Tegra20 and Tegra30.
>
> Changelog:
>
> v4: In the comment to v3 Peter De Schrijver pointed
On Tue, May 28, 2019 at 04:08:50PM -0700, Sowjanya Komatineni wrote:
> This patch adds support for suspend and resume for DFLL clock.
>
> Signed-off-by: Sowjanya Komatineni
> ---
> drivers/clk/tegra/clk-dfll.c | 82
>
> drivers/clk/tegra/clk-dfll.h |
On Fri, May 31, 2019 at 03:33:41PM +0300, Dmitry Osipenko wrote:
> 31.05.2019 11:26, Peter De Schrijver пишет:
> > On Fri, May 24, 2019 at 06:32:45PM +0300, Dmitry Osipenko wrote:
> >> Hello,
> >>
> >> This series primarily unifies the driver code across all Teg
On Fri, May 24, 2019 at 06:32:45PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series primarily unifies the driver code across all Tegra SoC
> generations. In a result the clocksources are allocated per-CPU on
> older Tegra's and have a higher rating than the arch-timer, the newer
> Tegra210 i
; > drivers/clk/tegra/clk-tegra124.c | 3 +--
> > 2 files changed, 3 insertions(+), 4 deletions(-)
> >
>
> Hello Peter,
>
> The patches in this series are trivial and fixing the longstanding bug on
> Tegra124. Could you ple
On Fri, Apr 12, 2019 at 02:02:21AM +0300, Dmitry Osipenko wrote:
> Add Add External Memory Controller node to the device-tree.
>
> Signed-off-by: Dmitry Osipenko
> ---
..
> diff --git a/drivers/memory/tegra/tegra30-emc.c
> b/drivers/memory/tegra/tegra30-emc.c
> index 38ebdb076ccd..defdb38bde54 1
On Fri, Apr 12, 2019 at 02:02:21AM +0300, Dmitry Osipenko wrote:
> Add Add External Memory Controller node to the device-tree.
>
One 'Add' is enough I think :)
Peter.
> Signed-off-by: Dmitry Osipenko
> ---
> arch/arm/boot/dts/tegra30.dtsi | 11 +++
> drivers/memory/tegra/tegra30-e
On Fri, Apr 12, 2019 at 01:47:08AM +0300, Dmitry Osipenko wrote:
> A proper External Memory Controller clock rounding and parent selection
> functionality is required by the EMC drivers. It is not available using
> the generic clock implementation, hence add a custom one. The clock rate
> rounding
t; Peter (and everyone else), yours r-b and ACK will be appreciated since you
> kinda already took a look at this patch in the past and were okay with it
> (IIRC, we had some brief discussion on the #tegra IRC a few months ago),
> thanks.
>
Acked-By: Peter De Schrijver
On Wed, Jan 30, 2019 at 10:40:06AM +0800, Joseph Lo wrote:
> On 1/29/19 6:29 PM, Thierry Reding wrote:
> > On Tue, Jan 29, 2019 at 10:41:55AM +0200, Peter De Schrijver wrote:
> > > On Mon, Jan 28, 2019 at 04:09:08PM +0100, Thierry Reding wrote:
> > >
> > > ..
On Mon, Jan 28, 2019 at 04:09:08PM +0100, Thierry Reding wrote:
...
>
> Up to here this is a duplicate of timer-tegra20.c. And a lot of
> tegra210_timer_init() is the same as tegra20_timer_init() as well. Can't
> we unify the two drivers instead?
>
> The power cycle restrictions of the architec
On Thu, Nov 01, 2018 at 02:52:29AM +0100, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> As UARTB and VFIR share their clock enable bit it is rather unwise for
> the kernel to turn off the VFIR one should that be unused (and
> potentially vice versa but so far there anyway is no VFIR driver).
On Mon, Sep 24, 2018 at 03:18:04PM -0400, r yang wrote:
> On Mon, Sep 24, 2018 at 11:08:03AM +0300, Peter De Schrijver wrote:
> > On Fri, Sep 21, 2018 at 06:01:49PM -0400, ryang wrote:
> > > The current behavior is that clk_round_rate would return the same clock
> > >
On Fri, Sep 21, 2018 at 06:01:49PM -0400, ryang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: ryang
> -
On Fri, Sep 21, 2018 at 06:00:37PM -0400, ryang wrote:
> Calling clk_set_rate or clk_round_rate will lock up the kernel when the
> rate is zero. This avoids the infinite loop and uses a slightly more
> optimized p divider calculation.
>
Acked-By: Peter De Schrijver
At some point we
On Fri, Aug 31, 2018 at 12:45:17PM +0300, Dmitry Osipenko wrote:
> On 8/31/18 12:29 PM, Peter De Schrijver wrote:
> > On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
> >> Currently all PLL's on Tegra20 use a hardcoded delay despite of having
> >> a
On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
> Currently all PLL's on Tegra20 use a hardcoded delay despite of having
> a lock-status bit. The lock-status polling was disabled ~7 years ago
> because PLLE was failing to lock and was a suspicion that other PLLs
> might be faulty t
On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote:
>
>
> On 2018-07-23 09:50, Peter De Schrijver wrote:
> >On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> >>The host1x clock according to both tegra2 and tegra3 manuals is
> >>an 8bit divider w
On Fri, Jul 20, 2018 at 02:45:27PM +0100, Ben Dooks wrote:
> The clocks vde, vi, epp, mpe, 2d and 3d are all fractional
> divisors, and not integer divisors as setup in the current
> kernel. This seems to be the same for tegra2 and tegra3.
>
Same comment as the host1x clock patch.
> Signed-off-b
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> The host1x clock according to both tegra2 and tegra3 manuals is
> an 8bit divider with lsb being fractional. This is running into
> an issue where the host1x is being set on a tegra20a system to
> 266.4MHz but ends up at 222MHz instead.
>
On Thu, Jul 12, 2018 at 11:52:31AM +0100, Jon Hunter wrote:
>
> On 11/07/18 15:39, Aapo Vienamo wrote:
> > From: Peter De-Schrijver
> >
> > Add a clock type to model the sdmmc switch divider clocks which have paths
> > to source clocks bypassing the divider (Lo
On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:
>
> On 11/07/18 09:00, Peter De Schrijver wrote:
> > On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
> >>
> >> On 09/07/18 17:38, Aapo Vienamo wrote:
> >>> From: Peter De Schrijver
&
On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>
> On 09/07/18 17:38, Aapo Vienamo wrote:
> > From: Peter De Schrijver
> >
> > Move this to a separate file so it can be used to calculate the sdmmc
> > clock dividers.
>
> Sorry for not commentin
Series Acked-By: Peter De Schrijver
Peter.
On Mon, Jul 09, 2018 at 07:38:54PM +0300, Aapo Vienamo wrote:
> The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a
> divider to achieve better jitter performance with high speed signaling
> modes. The clock path with the d
On Fri, Jul 06, 2018 at 11:18:30AM -0700, Stephen Boyd wrote:
> Quoting Aapo Vienamo (2018-07-04 03:17:34)
> > diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c
> > b/drivers/clk/tegra/clk-sdmmc-mux.c
> > new file mode 100644
> > index 000..8e19cb3
> > --- /dev/null
> > +++ b/drivers/clk/tegra/cl
On Wed, Jul 04, 2018 at 01:17:33PM +0300, Aapo Vienamo wrote:
> From: Peter De Schrijver
>
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.
>
Series Acked-By: Peter De Schrijver
> Signed-off-by: Peter De-Schrijver
> Signed
On Mon, Jun 04, 2018 at 01:48:05AM +0300, Dmitry Osipenko wrote:
> Memory Controller should be always-on. Currently the sibling EMC clock is
> marked as critical, let's mark MC clock too for consistency.
>
> Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
>
cument interrupt property
> ARM: dts: tegra20: Add interrupt to External Memory Controller
> clk: tegra20: Turn EMC clock gate into divider
> clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
> memory: tegra: Introduce Tegra20 EMC driver
>
Series Acked-By: Peter De Schrijver
On Tue, May 29, 2018 at 03:19:47PM +0300, Dmitry Osipenko wrote:
> On 29.05.2018 15:12, Stefan Agner wrote:
> > On 29.05.2018 09:48, Peter De Schrijver wrote:
> >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
> >>> On 28.05.2018 09:55, Peter De Schri
On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
> On 28.05.2018 09:55, Peter De Schrijver wrote:
> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
> >> From: Lucas Stach
> >>
> >> Set up the NAND Flash controller clock to run at 15
On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
> From: Lucas Stach
>
> Set up the NAND Flash controller clock to run at 150MHz
> instead of the rate set by the bootloader. This is a
> conservative rate which also yields good performance.
>
> Signed-off-by: Lucas Stach
> Signed-of
On Thu, May 24, 2018 at 03:49:22PM +0300, Dmitry Osipenko wrote:
> On 24.05.2018 13:04, Peter De Schrijver wrote:
> > On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote:
> >> PLL_C is running at 600MHz which is significantly higher than the 216MHz
> >> o
On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote:
> PLL_C is running at 600MHz which is significantly higher than the 216MHz
> of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is
> running on that PLL. Let's use PLL_C as intermediate clock source, making
> CPU sna
> get an orphaned clock. That might be undesirable because user may expect
> parent clock to be enabled by the child, so let's return -EPROBE_DEFER
> till parent clock appears.
>
> Signed-off-by: Dmitry Osipenko
On Fri, May 04, 2018 at 01:55:36AM +0300, Dmitry Osipenko wrote:
> CDEV1 and CDEV2 clocks are a bit special case, their parent clock is
> created by the pinctrl driver. It should be possible for clk user to
> request these clocks before pinctrl driver got probed and hence user will
> get an orphane
On Fri, Apr 27, 2018 at 02:58:15AM +0300, Dmitry Osipenko wrote:
> CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
> a parent. Add these dividers in order to be able to provide that parent
> option.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/clk/tegra/clk-tegra20.
orresponding muxes to fix the parents.
>
> Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
> ---
> drivers/clk/tegra/clk-tegra20.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/driver
rl_probe(struct platform_device *pdev)
> {
> - return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
> + int err;
> +
> + err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
> + if (err)
> + return err;
> +
> + tegra20_pinctrl_register_clock_muxes(pdev);
> +
> + return 0;
> }
>
> static const struct of_device_id tegra20_pinctrl_of_match[] = {
Apart from these nitpicks:
Acked-By: Peter De Schrijver
On Tue, Apr 24, 2018 at 05:38:41PM +0300, Dmitry Osipenko wrote:
> Hi Marcel,
>
> On 24.04.2018 01:05, Marcel Ziswiler wrote:
> > Hi Dmitry
> >
> > On Fri, 2018-04-20 at 13:50 +0300, Dmitry Osipenko wrote:
> >> ...
> >> I managed to find CDEV clocks in TRM this time.
> >
> > And where exactly in
On Mon, Mar 12, 2018 at 12:15:22PM +, Jon Hunter wrote:
>
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> > support in this driver. Also allow for the case where the CPU voltage is
> > control
On Mon, Mar 12, 2018 at 10:14:17AM +, Jon Hunter wrote:
>
> On 09/03/18 08:14, Peter De Schrijver wrote:
> > On Thu, Mar 08, 2018 at 11:25:04PM +, Jon Hunter wrote:
> >>
> >> On 06/02/18 16:34, Peter De Schrijver wrote:
> >>> Tegra210 has a very
On Mon, Mar 12, 2018 at 11:08:51AM +, Jon Hunter wrote:
>
> On 12/03/18 09:14, Peter De Schrijver wrote:
> > On Thu, Mar 08, 2018 at 10:50:06PM +, Jon Hunter wrote:
> >>
> >> On 06/02/18 16:34, Peter De Schrijver wrote:
> >>> This patch prepares t
On Thu, Mar 08, 2018 at 10:50:06PM +, Jon Hunter wrote:
>
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > This patch prepares the dfll driver to work with PWM regulators.
> > To do this we introduce a new array lut_uv which gives the voltage for
> > a given ind
On Thu, Mar 08, 2018 at 11:21:40PM +, Jon Hunter wrote:
>
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > Add new properties to configure the DFLL PWM regulator support. Also
> > add an example and make the I2C clock only required when I2C support is
> > used.
>
On Thu, Mar 08, 2018 at 11:25:04PM +, Jon Hunter wrote:
>
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> > support in this driver. Also allow for the case where the CPU voltage is
> > control
On Thu, Mar 08, 2018 at 11:15:17PM +, Jon Hunter wrote:
>
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > The DFLL can directly generate a PWM signal to control the regulator IC
> > rather then sending i2c messages. This patch adds support for this mode.
> > In th
On Fri, Mar 02, 2018 at 09:02:07AM +, Jon Hunter wrote:
>
> On 01/03/18 07:41, Peter De Schrijver wrote:
> > On Wed, Feb 28, 2018 at 08:20:47PM +0300, Dmitry Osipenko wrote:
> >> On 28.02.2018 17:14, Peter De Schrijver wrote:
> >>> On Wed, Feb 28, 2018 at
On Wed, Feb 28, 2018 at 08:20:47PM +0300, Dmitry Osipenko wrote:
> On 28.02.2018 17:14, Peter De Schrijver wrote:
> > On Wed, Feb 28, 2018 at 03:00:23PM +0300, Dmitry Osipenko wrote:
> >> On 28.02.2018 12:36, Peter De Schrijver wrote:
> >>> On Tue, Feb 27, 2018 at 02:
On Wed, Feb 28, 2018 at 03:00:23PM +0300, Dmitry Osipenko wrote:
> On 28.02.2018 12:36, Peter De Schrijver wrote:
> > On Tue, Feb 27, 2018 at 02:59:11PM +0300, Dmitry Osipenko wrote:
> >> On 27.02.2018 02:04, Marcel Ziswiler wrote:
> >>> On Mon, 2018-02-26 at 15:4
On Tue, Feb 27, 2018 at 02:59:11PM +0300, Dmitry Osipenko wrote:
> On 27.02.2018 02:04, Marcel Ziswiler wrote:
> > On Mon, 2018-02-26 at 15:42 +0300, Dmitry Osipenko wrote:
> >> On 23.02.2018 02:04, Marcel Ziswiler wrote:
> >>> Turns out latest upstream U-Boot does not configure/enable pllu
> >>> w
On Tue, Feb 13, 2018 at 11:30:39AM +0100, Thierry Reding wrote:
> > }
>
> It's odd that we don't have an MC clock on Tegra2. I wonder if perhaps
> we just never implemented one, or it uses one which is always on by
> default. Cc Peter to see if he knows.
We do, it has DT ID TEGRA20_CLK_MC. Ho
On Wed, Feb 07, 2018 at 03:01:55PM +, Mark Brown wrote:
> On Wed, Feb 07, 2018 at 04:32:13PM +0200, Peter De Schrijver wrote:
> > On Wed, Feb 07, 2018 at 02:18:46PM +, Mark Brown wrote:
>
> > > You're going to have to provide a much better explanation of what t
On Wed, Feb 07, 2018 at 02:18:46PM +, Mark Brown wrote:
> On Wed, Feb 07, 2018 at 02:37:51PM +0200, Peter De Schrijver wrote:
> > On Wed, Feb 07, 2018 at 10:43:51AM +, Mark Brown wrote:
> > > On Wed, Feb 07, 2018 at 10:47:44AM +0200, Peter De Schrijver wrote:
> >
On Wed, Feb 07, 2018 at 10:43:51AM +, Mark Brown wrote:
> On Wed, Feb 07, 2018 at 10:47:44AM +0200, Peter De Schrijver wrote:
> > On Tue, Feb 06, 2018 at 04:35:44PM +, Mark Brown wrote:
> > > On Tue, Feb 06, 2018 at 06:34:02PM +0200, Peter De Schrijver wrote:
>
>
On Tue, Feb 06, 2018 at 04:35:44PM +, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Tue, Feb 06, 2018 at 06:34:02PM +0200, Peter De Schrijver wrote:
> > From: Laxman Dewangan
> >
> > Add API to get min/max rail voltage configured from platform for
&g
also changing the DFLL output frequency. Also the register debugfs
file is slightly reworked to only show the i2c registers when i2c mode is
in use. As there is no regulator object for the PWM regulator, its step and
offset values are retrieved from DT instead.
Signed-off-by: Peter De Schrijver
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 37 --
1 file changed, 30
From: Laxman Dewangan
Add API to get min/max rail voltage configured from platform for
given rails.
Changes to the commit message by
Peter De Schrijver
Signed-off-by: Laxman Dewangan
---
drivers/regulator/core.c | 31 +++
include/linux/regulator
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 426 +
drivers/clk/tegra/cvb.h| 1 +
2 files changed, 427 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
b/drivers/clk/tegra/clk-tegra124
allowed taking temperature
into accouint. Also this will be updated dynamically once temperature
dependence will be introduced.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-dfll.c | 62 ++--
1 file changed, 37 insertions(+), 25 deletions(-)
diff
Signed-off-by: Peter De Schrijver
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index bc9851a..a7fddae 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210
Signed-off-by: Peter De Schrijver
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 18 ++
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 12
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++
3 files changed, 49 insertions(+)
diff --git a
Add new properties to configure the DFLL PWM regulator support. Also
add an example and make the I2C clock only required when I2C support is
used.
Signed-off-by: Peter De Schrijver
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 76 +-
1 file changed, 74 insertions
Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
support in this driver. Also allow for the case where the CPU voltage is
controlled directly by the DFLL rather than by a separate regulator object.
Signed-off-by: Peter De Schrijver
---
drivers/cpufreq/tegra124-cpufreq.c
Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/Kconfig | 5 +
drivers/clk/tegra/Makefile | 2 +-
2 files changed, 6 insertions(+), 1
regulator framework and store them as part of the
tegra_dfll_soc_data struct.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-dfll.h | 2 ++
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 42 +-
drivers/clk/tegra/cvb.c| 16
Laxman Dewangan (1):
regulator: core: add API to get voltage constraints
Peter De Schrijver (10):
clk: tegra: retrieve regulator info from framework
clk: tegra: dfll registration for multiple SoCs
clk: tegra: add CVB tables for Tegra210 CPU DFLL
clk: tegra: prepare dfll driver for PWM regul
On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote:
> On 12.12.2017 13:02, Peter De Schrijver wrote:
> > On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote:
> >> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but
> >> clock
On Mon, Dec 11, 2017 at 09:50:11PM +0300, Dmitry Osipenko wrote:
> Currently VDE clock rate is determined by clock config left from
> bootloader, let's not rely on it and explicitly specify the clock
> rate in the CCF driver.
>
> Signed-off-by: Dmitry Osipenko
Acked-By
On Mon, Dec 11, 2017 at 09:50:12PM +0300, Dmitry Osipenko wrote:
> PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
> set it to 240 MHz and explicitly specify HCLK rate for consistency.
>
> Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
and
> PLL_P outputs. Let's mark MC or PLL_P outputs as critical for now and
> revert this change once drivers would be corrected.
>
> Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
> ---
> drivers/clk/tegra/clk-divider.c | 3 ++-
>
On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote:
> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but
> clock driver doesn't provide that rate, so the requested clock is rounded
> up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq.
>
This seems od
t;
> Signed-off-by: Nicolin Chen
Acked-By: Peter De Schrijver
> ---
>
> As I don't have a T124 platform, I can't verify it on a board.
> If someone could provide a Tested-by, it would be very helpful.
> The test could be a simple system suspend/resume that acti
Acked-By: Peter De Schrijver
I would assume this also applies to many PLL structs for other Tegra SoCs?
Peter.
On Tue, Oct 03, 2017 at 01:42:08AM +0530, Bhumika Goyal wrote:
> These structures are only passed to the functions tegra_clk_register_pll,
> tegra_clk_register_pll{e
Acked-By: Peter De Schrijver
On Wed, Sep 27, 2017 at 06:53:10PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Wed, 27 Sep 2017 18:40:34 +0200
>
> Omit extra messages for a memory allocation failure in these functions.
>
> This issue was detected by us
On Tue, Sep 26, 2017 at 05:46:01PM +0300, Dmitry Osipenko wrote:
> On 26.09.2017 12:56, Peter De Schrijver wrote:
> > On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:
> >> AHB DMA presents on Tegra20/30. Add missing entries, so that driver
> >> for A
On Tue, Sep 26, 2017 at 02:22:03AM +0300, Dmitry Osipenko wrote:
> AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate
> results in an increased DMA transfer rate.
>
> Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
> ---
> drivers/clk/t
On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:
> AHB DMA presents on Tegra20/30. Add missing entries, so that driver
> for AHB DMA could be implemented.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/clk/tegra/clk-id.h | 1 +
> drivers/clk/tegra/clk-tegra-periph.c
Apart from the typo in the commit message (preemption rather than preemtion):
Acked-By: Peter De Schrijver
On Thu, Sep 14, 2017 at 06:36:14PM -0700, Nicolin Chen wrote:
> Below is the call trace of tegra210_init_pllu() function:
> start_kernel()
> -> time_init()
>
On Tue, Jul 25, 2017 at 06:37:46PM -0700, Stephen Boyd wrote:
> On 07/25, Peter De Schrijver wrote:
> > A number of smaller fixes and simplifications for the Tegra clock
> > implementation.
>
> Any of these need fixes tags so they can be backported to stable
> trees? Also,
On Tue, Jul 25, 2017 at 05:32:08PM -0700, Stephen Boyd wrote:
> On 07/25, Peter De Schrijver wrote:
> > From: Alex Frid
> >
> > Add a check for error returned by divider value calculation to avoid
> > writing error code into hw register.
> >
> > Signed-of
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