The following commit has been merged into the timers/core branch of tip:
Commit-ID: 48016e78d328998b1f00bcfb639adeabca51abe5
Gitweb:
https://git.kernel.org/tip/48016e78d328998b1f00bcfb639adeabca51abe5
Author:Paul Burton
AuthorDate:Thu, 21 May 2020 23:48:16 +03:00
Hello,
On Thu, May 21, 2020 at 6:04 PM Maciej W. Rozycki wrote:
> Paul may or may not be reachable anymore, so I'll step in.
I'm reachable but lacking free time & with no access to Malta hardware
I can't claim to be too useful here, so thanks for responding :)
Before being moved to a driver (w
mmediately precede the MFC0 - it simply
needs to be between the MTC0 & MFC0.
This bug only affects Cavium Octeon systems which use
build_fast_tlb_refill_handler().
Signed-off-by: Paul Burton
Fixes: 0b24cae4d535 ("MIPS: Add missing EHB in mtc0 -> mfc0 sequence.")
Cc: Dmitry
Hello,
Paul Burton wrote:
> From: Paul Burton
>
> Switch to using my paulbur...@kernel.org email address in order to avoid
> subject mangling that's being imposed on my previous address.
Applied to mips-fixes.
> commit 0ad8f7aa9f7e
> https://git.kernel.org/mips/c/0ad8f
From: Paul Burton
Switch to using my paulbur...@kernel.org email address in order to avoid
subject mangling that's being imposed on my previous address.
Signed-off-by: Paul Burton
Signed-off-by: Paul Burton
---
.mailmap| 3 ++-
MAINTAINERS | 10 +-
2 files changed, 7 inser
Hi Tiezhu & Huacai,
On Tue, Oct 15, 2019 at 12:00:25PM +0800, Tiezhu Yang wrote:
> On 10/15/2019 11:36 AM, Huacai Chen wrote:
> > On Tue, Oct 15, 2019 at 10:12 AM Tiezhu Yang wrote:
> > > When I update kernel with loongson3_defconfig based on the Loongson 3A3000
> > > platform, then using dmesg c
Hi Geert, Greg,
On Mon, Oct 14, 2019 at 09:04:21AM +0200, Geert Uytterhoeven wrote:
> On Mon, Oct 14, 2019 at 8:53 AM Geert Uytterhoeven
> wrote:
> > JFYI, when comparing v5.4-rc3[1] to v5.4-rc2[3], the summaries are:
> > - build errors: +1/-0
>
> + /kisskb/src/drivers/staging/octeon/ethern
cess in firmware handling code for old SNI
RM200/300/400 machines.
Jiaxun Yang (1):
MIPS: elf_hwcap: Export userspace ASEs
Paul Burton (1):
MIPS: Disable Loongson MMI instructions for kernel build
Thomas Bogendoerfe
ang 9.0.0
> has no issues after this change.
Applied to mips-next.
> commit df3da04880b4
> https://git.kernel.org/mips/c/df3da04880b4
>
> Fixes: 6baaeadae911 ("MIPS: Provide unroll() macro, use it for cache ops")
> Link: https://github.com/ClangBuiltLinux/linux/issues/7
e93
> https://git.kernel.org/mips/c/d11646b5ce93
>
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Paul Burton
>
> MIPS: fw: arc: use call_o32 to call ARC prom from 64bit kernel
> commit ce6c0a593b3c
> https://git.kernel.org/mips/c/ce6c0a593b3c
>
>
Hello,
Thomas Bogendoerfer wrote:
> Use ARRAY_SIZE to caluculate the top of the o32 stack.
Applied to mips-fixes.
> commit efcb529694c3
> https://git.kernel.org/mips/c/efcb529694c3
>
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Paul Burton
Thanks,
Paul
[ Thi
er, which is an error case
> for catching bugs and will not happen for correct code, if
> __xchg is inlined.
Applied to mips-fixes.
> commit 46f1619500d0
> https://git.kernel.org/mips/c/46f1619500d0
>
> Signed-off-by: Thomas Bogendoerfer
> Reviewed-by: Philippe Mathieu-Daudé
&g
a const void *mach_match_data;
Applied to mips-next.
> commit a14bf1dc494a
> https://git.kernel.org/mips/c/a14bf1dc494a
>
> Fixes: eed0eabd12ef ("MIPS: generic: Introduce generic DT-based board
> support")
> Signed-off-by: Tiezhu Yang
> Signed-off-by: Paul Bur
other
common asm/ headers.
Signed-off-by: Paul Burton
Reported-by: Geert Uytterhoeven
URL:
https://lore.kernel.org/linux-mips/CAMuHMdXvu+BppwzsU9imNWVKea_hoLcRt9N+a29Q-QsjW=i...@mail.gmail.com/
Fixes: 171a9bae68c7 ("staging/octeon: Allow test build on !MIPS")
Cc: Matthew Wilcox (Oracle)
/c/9662dd752c14
>
> Signed-off-by: Aurabindo Jayamohanan
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.bur...@mips.com to report it. ]
Hello,
Alexandre GRIVEAUX wrote:
> Adding leds and related triggers.
Applied to mips-next.
> commit 24b0cb4f883a
> https://git.kernel.org/mips/c/24b0cb4f883a
>
> Signed-off-by: Alexandre GRIVEAUX
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto
Hello,
Alexandre GRIVEAUX wrote:
> Add IW8103 Wifi + bluetooth module to device tree and related power domain.
Applied to mips-next.
> commit 948f2708f945
> https://git.kernel.org/mips/c/948f2708f945
>
> Signed-off-by: Alexandre GRIVEAUX
> Signed-off-by: Paul Burton
Thanks
Hello,
Alexandre GRIVEAUX wrote:
> Adding missing I2C nodes and some peripheral:
> - PMU
> - RTC
Applied to mips-next.
> commit 73f2b940474d
> https://git.kernel.org/mips/c/73f2b940474d
>
> Signed-off-by: Alexandre GRIVEAUX
> Signed-off-by: Paul Burton
Thanks,
46a73e9e6ccc
> https://git.kernel.org/mips/c/46a73e9e6ccc
>
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Paul Burton
>
> MIPS: SGI-IP27: get rid of compact node ids
> commit 4bf841ebf17a
> https://git.kernel.org/mips/c/4bf841ebf17a
>
> Signed-o
Hello,
Alexandre GRIVEAUX wrote:
> Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled
> by default.
Applied to mips-next.
> commit f56a040c9faf
> https://git.kernel.org/mips/c/f56a040c9faf
>
> Signed-off-by: Alexandre GRIVEAUX
> Signed-off-by: Paul Burt
s Bogendoerfer
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Mike Rapoport
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.bur...@mips.com to report it. ]
Hello,
Paul Burton wrote:
> This series consists of a bunch of cleanups to the way we handle memory
> barriers (though no changes to the sync instructions we use to implement
> them) & atomic memory accesses. One major goal was to ensure the
> Loongson3 LL/SC errata workarounds
ter, which is a error case
> for catching bugs and will not happen for correct code, if
> __cmpxchg is inlined.
Applied to mips-fixes.
> commit 88356d09904b
> https://git.kernel.org/mips/c/88356d09904b
>
> Signed-off-by: Thomas Bogendoerfer
> [paul.bur...@mips.com: s/__cmpxc
m_map
Jiaxun Yang (1):
MIPS: cpu-bugs64: Mark inline functions as __always_inline
Oleksij Rempel (1):
MIPS: dts: ar9331: fix interrupt-controller size
Paul Burton (7):
MIPS: octeon: Include required header; fix octeon ethernet build
MIPS: Wire up clone3 syscall
MIPS
in struct nand_chip is 0
making mtd_to_nand() effectively a type-cast.
Signed-off-by: Paul Burton
Fixes: 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx()
hooks")
Cc: Boris Brezillon
Cc: Miquel Raynal
Cc: David Woodhouse
Cc: Brian Norris
Cc: Mar
in struct nand_chip is 0
making mtd_to_nand() effectively a type-cast.
Signed-off-by: Paul Burton
Fixes: 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx()
hooks")
Cc: Boris Brezillon
Cc: Miquel Raynal
Cc: David Woodhouse
Cc: Brian Norris
Cc: Mar
fixes.
> commit bd848d1b9235
> https://git.kernel.org/mips/c/bd848d1b9235
>
> Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map")
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto-generated; if you believe anythin
m_map")
> Signed-off-by: Thomas Bogendoerfer
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.bur...@mips.com to report it. ]
")
> Signed-off-by: Christophe JAILLET
> Signed-off-by: Paul Burton
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.bur...@mips.com to report it. ]
Hi Geert,
On Wed, Oct 02, 2019 at 11:17:26AM +0200, Geert Uytterhoeven wrote:
> > 15 error regressions:
> > + /kisskb/build/tmp/cc1Or5dj.s: Error: can't resolve `_start' {*UND*
> > section} - `L0 ' {.text section}: => 663, 1200, 222, 873, 1420
> > + /kisskb/build/tmp/cc2uWmof.s: Error: can't
Hi Alexandre,
On Tue, Oct 01, 2019 at 09:09:48PM +0200, Alexandre GRIVEAUX wrote:
> The JZ4780 have 2 core, adding to DT.
>
> Signed-off-by: Alexandre GRIVEAUX
> ---
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/mips/b
ptimized memory barrier primitives."). Using
__SYNC() with the wmb or rmb types will abstract away the Octeon
specific behavior and allow us to later clean up asm/barrier.h code that
currently includes a plethora of #ifdef's.
Signed-off-by: Paul Burton
---
Changes in v2:
Rather than #ifdef on CONFIG_CPU_* to determine whether the ins
instruction is supported we can simply check MIPS_ISA_REV to discover
whether we're targeting MIPSr2 or higher. Do so in order to clean up the
code.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/includ
avior anyway.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 657ec01120a4..a117c6d95038 100644
--- a/arch
We define macros in asm/atomic.h which end each line with space
characters before a backslash to continue on the next line. Remove the
space characters leaving tabs as the whitespace used for conformity with
coding convention.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips
We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.
Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.
Signed-off-by: Paul Bu
When targeting MIPSr6 or higher make use of a compact branch in LL/SC
loops, preventing the insertion of a delay slot nop that only serves to
waste space.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/llsc.h | 4
1 file changed, 4 insertions(+)
diff --git a
all other functions in asm/atomic.h are
generated, and ensures consistency between the 32b & 64b functions.
Of note is that this results in the above now being static inline
functions rather than macros.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/atomi
Handle the !kernel_uses_llsc path first in our ATOMIC_OP(),
ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros & return from within the
block. This allows us to de-indent the kernel_uses_llsc path by one
level which will be useful when making further changes.
Signed-off-by: Paul Burton
---
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch
The loongson_llsc_mb() macro is no longer used - instead barriers are
emitted as part of inline asm using the __SYNC() macro. Remove the
now-defunct loongson_llsc_mb() macro.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 40
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
Changes in v2:
- De-string __WEAK_LLSC_MB to allow its use with __SYNC_ELSE().
arch/mips/include/asm/barrier.h | 13 +++--
arch/mips/include/asm/futex.h | 15 +++
2 files changed
duce code
paths that miss the required workarounds.
Signed-off-by: Paul Burton
---
Changes in v2:
- Only try to build loongson3-llsc-check from arch/mips/Makefile when
CONFIG_CPU_LOONGSON3_WORKAROUNDS is enabled.
arch/mips/Makefile | 3 +
arch/mips/Makefile
The logical operations or & xor used in the test_and_set_bit_lock(),
test_and_clear_bit() & test_and_change_bit() functions currently force
the value 1<
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mi
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/kernel/syscall.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index b0e25e913bdb..3ea288ca35f1 10
rious implementations, we switch to returning from within each
if block making each case easier to read in isolation.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 213 -
1 file changed, 105 insertions(+), 108 deletions(-)
rier within __test_bit_op().
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index c08b6d225f10..a74769940fbd 100644
--- a/
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
emit a full completion barrier as part of the inline assembly containing
LL/SC loops for atomic operations. As such the barrier emitted by
__smp_mb__before_atomic() is redundant, and we can remove it.
Signed-off-by: Paul
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index d39fca2d
t1, t1, 0x10
sc t1, 0(t2)
The or path already allows immediates to be used, so simply restricting
the ins path to bits that don't fit in immediates is sufficient to take
advantage of this.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 2 +-
1 fil
ed by raw_local_irq_{save,restore}().
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 24
arch/mips/include/asm/llsc.h | 4
arch/mips/lib/bitops.c | 31 +--
3 files changed, 25 insertions(+), 34
In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.
Signed-off-by: Pau
Use the BIT() macro in asm/bitops.h rather than open-coding its
equivalent.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b
Introduce __bit_op() & __test_bit_op() macros which abstract away the
implementation of LL/SC loops. This cuts down on a lot of duplicate
boilerplate code, and also allows R1_LLSC_WAR to be handled outside
of the individual bitop functions.
Signed-off-by: Paul Burton
---
Changes in v2:
cros. Add compile-time constant checks causing us to omit the
redundant memory barriers.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/cmpxchg.h | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/cmpxchg.h | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
i
tion of the extra memory barrier.
Do this in order to avoid duplicating logic.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 66 +++---
arch/mips/lib/bitops.c | 26 --
2 files changed, 13 insertions(+)
er memory accesses & therefore
isn't affected by Loongson3 LL/SC errata.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/kernel/genex.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac4f2b83
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/atomic.h | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
i
Use smp_mb__before_atomic() & smp_mb__after_atomic() in
atomic_sub_if_positive() rather than the equivalent
smp_mb__before_llsc() & smp_llsc_mb(). The former are more standard &
this preps us for avoiding redundant duplicate barriers on Loongson3 in
a later patch.
Signed-off-by:
for sanity.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 0f5329e32e87..03532ae9f528 100644
--- a/arch/mips/include/as
Use the new __SYNC() infrastructure to implement sync_ginv(), for
consistency with much of the rest of the asm/barrier.h.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include
the atomic64_sub_if_positive() case which were
previously missing.
The code is rearranged a little to handle the !kernel_uses_llsc case
first in order to de-indent the LL/SC case & allow us not to go over 80
characters per line.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/
ef'ery is removed, since the "syncw" instruction
previously used is merely an alias for "sync 4" which __SYNC() will emit
for the wmb sync type when the kernel is configured for an Octeon CPU.
Similarly __SYNC() will emit nothing for the rmb sync type in Octeon
c
Cut down on duplication by generalizing the ATOMIC_OP(),
ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros to work for both 32b &
64b atomics, and removing the ATOMIC64_ variants. This ensures
consistency between our atomic_* & atomic64_* functions.
Signed-off-by: Paul Burton
---
C
include whitespace of their own after the
instruction mnemonic.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/atomic.h | 28 +---
arch/mips/include/asm/cmpxchg.h | 20
arch/mips/include/asm/llsc.h| 11 +++
'd need to go implement
those then using the generic fls/ffs doesn't seem like such a win.
- De-string __WEAK_LLSC_MB to allow use with __SYNC_ELSE().
- Only try to build the loongson3-llsc-check tool from
arch/mips/Makefile when CONFIG_CPU_LOONGSON3_WORKAROUNDS is enabled.
Paul Burton (36)
The definition of fast_mb() is the same in both the Octeon & non-Octeon
cases, so remove the duplication & define it only once.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/a
When targeting MIPSr6 or higher make use of a compact branch in LL/SC
loops, preventing the insertion of a delay slot nop that only serves to
waste space.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/llsc.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/include/asm
ptimized memory barrier primitives."). Using
__SYNC() with the wmb or rmb types will abstract away the Octeon
specific behavior and allow us to later clean up asm/barrier.h code that
currently includes a plethora of #ifdef's.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/barrier.h |
t1, t1, 0x10
sc t1, 0(t2)
The or path already allows immediates to be used, so simply restricting
the ins path to bits that don't fit in immediates is sufficient to take
advantage of this.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 2 +-
1 file changed, 1 insert
The logical operations or & xor used in the test_and_set_bit_lock(),
test_and_clear_bit() & test_and_change_bit() functions currently force
the value 1<
---
arch/mips/include/asm/bitops.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/bitops
avior anyway.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/barrier.h | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 657ec01120a4..a117c6d95038 100644
--- a/arch/mips/includ
We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.
Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.
Signed-off-by: Paul Bu
Use smp_mb__before_atomic() & smp_mb__after_atomic() in
atomic_sub_if_positive() rather than the equivalent
smp_mb__before_llsc() & smp_llsc_mb(). The former are more standard &
this preps us for avoiding redundant duplicate barriers on Loongson3 in
a later patch.
Signed-off-by:
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/atomic.h | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index b834af5a
The loongson_llsc_mb() macro is no longer used - instead barriers are
emitted as part of inline asm using the __SYNC() macro. Remove the
now-defunct loongson_llsc_mb() macro.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/barrier.h | 40 -
arch/mips
for sanity.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b8785bdf3507..83fd1f1c3ab4 100644
--- a/arch/mips/include/asm/bitops.h
+++ b
er memory accesses & therefore
isn't affected by Loongson3 LL/SC errata.
Signed-off-by: Paul Burton
---
arch/mips/kernel/genex.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac4f2b835165..60ede6b75a3b 1006
In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.
Signed-off-by: Pau
cros. Add compile-time constant checks causing us to omit the
redundant memory barriers.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/cmpxchg.h | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/in
duce code
paths that miss the required workarounds.
Signed-off-by: Paul Burton
---
arch/mips/Makefile | 2 +-
arch/mips/Makefile.postlink| 10 +-
arch/mips/tools/.gitignore | 1 +
arch/mips/tools/Makefile | 5 +
arch/mips/tools/
Use the BIT() macro in asm/bitops.h rather than open-coding its
equivalent.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm
rier within __test_bit_op().
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9e967d6622c8..e6d97238a321 100644
--- a/arch/mips/include
e is the ability for kernels built to target a
pre-r1 ISA to opportunistically make use of clz when running on a CPU
that implements it. This seems like a small cost, and well worth paying
to simplify the code.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 59fe1d5d4fc9..9e967d6622c8 10
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
arch/mips/kernel/syscall.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index b0e25e913bdb..3ea288ca35f1 100644
--- a/arch/
rious implementations, we switch to returning from within each
if block making each case easier to read in isolation.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 213 -
1 file changed, 105 insertions(+), 108 deletions(-)
diff --git a/arch/mips/in
ed by raw_local_irq_{save,restore}().
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 24
arch/mips/include/asm/llsc.h | 4
arch/mips/lib/bitops.c | 31 +--
3 files changed, 25 insertions(+), 34 deletions(-)
diff
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/futex.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index b83b0397462d..45c3e3652f48 100644
-
had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/cmpxchg.h | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 5d3f0e3513b4..fc121d20
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
emit a full completion barrier as part of the inline assembly containing
LL/SC loops for atomic operations. As such the barrier emitted by
__smp_mb__before_atomic() is redundant, and we can remove it.
Signed-off-by: Paul
Use the new __SYNC() infrastructure to implement sync_ginv(), for
consistency with much of the rest of the asm/barrier.h.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/barrier.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch
Handle the !kernel_uses_llsc path first in our ATOMIC_OP(),
ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros & return from within the
block. This allows us to de-indent the kernel_uses_llsc path by one
level which will be useful when making further changes.
Signed-off-by: Paul Burton
--
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h
tion of the extra memory barrier.
Do this in order to avoid duplicating logic.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/bitops.h | 66 +++---
arch/mips/lib/bitops.c | 26 --
2 files changed, 13 insertions(+), 79 deletions(-)
diff --g
all other functions in asm/atomic.h are
generated, and ensures consistency between the 32b & 64b functions.
Of note is that this results in the above now being static inline
functions rather than macros.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/atomi
-asm & that we can automatically verify the resulting
kernel binary looks reasonable. Many patches are cleanups found along
the way.
Applies atop v5.4-rc1.
Paul Burton (37):
MIPS: Unify sc beqz definition
MIPS: Use compact branch for LL/SC loops on MIPSr6+
MIPS: barrier: Ad
Introduce __bit_op() & __test_bit_op() macros which abstract away the
implementation of LL/SC loops. This cuts down on a lot of duplicate
boilerplate code, and also allows R1_LLSC_WAR to be handled outside
of the individual bitop functions.
Signed-off-by: Paul Burton
---
arch/mips/inc
We define macros in asm/atomic.h which end each line with space
characters before a backslash to continue on the next line. Remove the
space characters leaving tabs as the whitespace used for conformity with
coding convention.
Signed-off-by: Paul Burton
---
arch/mips/include/asm/atomic.h | 184
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